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241 条记录 (耗时 0.044 秒)

    DC/low frequency sub-atto signal level measurement circuit
    41.
    发明授权
    DC/low frequency sub-atto signal level measurement circuit 有权
    直流/低频子信号电平测量电路

    公开(公告)号：US06556025B1

    公开(公告)日：2003-04-29

    申请号：US09595367

    申请日：2000-06-16

    申请人： Arokia Nathan ,  Yong Lu ,  Tajinder Manku

    发明人： Arokia Nathan ,  Yong Lu ,  Tajinder Manku

    IPC分类号： G01R2726

    CPC分类号： G01R19/2509 ,  G01R27/2605 ,  G01R29/24

    摘要： A method of measuring changes in signal level output of an integrated circuit sensor by providing a direct current (DC) or low frequency (AC) bias to the sensor and placing a floating gate semiconductor device on-chip and coupling the floating gate of the semiconductor device with the sensor. As a result, changes in signal level output of the sensor modulate charge at the gate. The semiconductor device in turn converts the modulated charge at the gate into output signals proportional to the changes in the signal level output. The measurement method provides a resolution in the sub-atto range.

    摘要翻译： 一种通过向传感器提供直流（DC）或低频（AC）偏压并且将浮置栅极半导体器件放置在芯片上并耦合半导体的浮置栅极来测量集成电路传感器的信号电平输出的变化的方法 设备与传感器。 结果，传感器的信号电平输出的变化调制门的电荷。 半导体器件又将栅极处的调制电荷转换为与信号电平输出的变化成比例的输出信号。 测量方法提供了分数范围内的分辨率。

    Method and apparatus for writing data states to non-volatile storage devices
    42.
    发明授权
    Method and apparatus for writing data states to non-volatile storage devices 有权
    将数据状态写入非易失性存储设备的方法和装置

    公开(公告)号：US06178111B1

    公开(公告)日：2001-01-23

    申请号：US09455850

    申请日：1999-12-07

    申请人： Jeffrey Scott Sather ,  Theodore Zhu ,  Yong Lu

    发明人： Jeffrey Scott Sather ,  Theodore Zhu ,  Yong Lu

    IPC分类号： G11C1100

    CPC分类号： G11C11/15

    摘要： Disclosed are apparatus and methods for efficiently writing states to one or more magneto-resistive elements. In one embodiment, current switches are provided for directing a write current through a number of write lines to control the write state of the magneto-resistive elements. In another embodiment, a sense current is selectively controlled to control which magneto-resistive elements are written to a particular state. In both embodiments, a latching element may be used to sense the state of the magneto-resistive elements, and may assume a corresponding logic state.

    摘要翻译： 公开了用于有效地将状态写入一个或多个磁阻元件的装置和方法。 在一个实施例中，提供电流开关用于引导写入电流通过多个写入线以控制磁阻元件的写入状态。 在另一个实施例中，选择性地控制感测电流以控制将哪个磁阻元件写入特定状态。 在两个实施例中，锁存元件可用于感测磁阻元件的状态，并且可以采取相应的逻辑状态。

    Bipolar CMOS select device for resistive sense memory
    44.
    发明授权
    Bipolar CMOS select device for resistive sense memory 有权
    用于电阻读出存储器的双极CMOS选择器件

    公开(公告)号：US09030867B2

    公开(公告)日：2015-05-12

    申请号：US12502211

    申请日：2009-07-13

    申请人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    发明人： Yong Lu ,  Hongyue Liu ,  Maroun Khoury ,  Yiran Chen

    IPC分类号： G11C11/00 ,  G11C11/34 ,  G11C13/00 ,  G11C11/16

    CPC分类号： G11C13/0004 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/76

    摘要： A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

    摘要翻译： 电阻式感测存储装置包括具有半导体衬底和设置在半导体衬底中并形成行或晶体管的多个晶体管的双极选择器件。 每个晶体管包括发射极触点和集电极触点。 每个集电极触点彼此电隔离，并且每个发射极触点彼此电隔离。 栅极触点沿发射极触点和集电极触点之间的沟道区域延伸。 基极触点设置在半导体衬底内，使得发射极触点和集电极触点位于栅极触点和基极触点之间。 电阻读出存储单元电耦合到每个集电极触点或发射极触点和位线。

    Optical transceiver integrated with optical time domain reflectometer monitoring
    45.
    发明授权
    Optical transceiver integrated with optical time domain reflectometer monitoring 有权
    光收发器集成了光时域反射仪监控

    公开(公告)号：US08942556B2

    公开(公告)日：2015-01-27

    申请号：US13309983

    申请日：2011-12-02

    申请人： Fuqiang Zhao ,  Yi Yang ,  Yong Lu

    发明人： Fuqiang Zhao ,  Yi Yang ,  Yong Lu

    IPC分类号： H04B10/08 ,  H04B10/272 ,  H04B10/071 ,  H04B10/40 ,  H04B10/00

    CPC分类号： H04B10/272 ,  H04B10/071 ,  H04B10/40

    摘要： An optical transceiver having an integrated optical time domain reflectometer monitoring unit and methods for using the same are disclosed. The disclosure relates to an optical transceiver comprising an optical device comprising a wavelength division multiplexing system (WDM), a data signal driver, a data signal limiting amplifier, and an optical time domain reflectometer (OTDR) data processing module. Furthermore, the optical transceiver is particularly advantageous in an optical line terminal (OLT) and/or a passive optical network (PON). The integrated OTDR data processing module can protect the optical transceiver, ensure successful monitoring data, simplify network wiring and decrease system and network costs by decreasing the number of OTDR modules and WDM units.

    摘要翻译： 公开了一种具有集成光时域反射计监视单元的光收发器及其使用方法。 本公开涉及一种光收发器，包括包括波分复用系统（WDM），数据信号驱动器，数据信号限幅放大器和光时域反射计（OTDR）数据处理模块的光学装置。 此外，光收发器在光线路终端（OLT）和/或无源光网络（PON）中是特别有利的。 集成的OTDR数据处理模块可以通过减少OTDR模块和WDM单元的数量来保护光收发器，确保成功监控数据，简化网络布线，降低系统和网络成本。

    Bit line charge accumulation sensing for resistive changing memory
    48.
    发明授权
    Bit line charge accumulation sensing for resistive changing memory 有权
    电阻变化存储器的位线电荷累积检测

    公开(公告)号：US08638597B2

    公开(公告)日：2014-01-28

    申请号：US13476368

    申请日：2012-05-21

    申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

    摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

    摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域电连接在r磁阻变化存储器单元和栅极之间。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。

    Magnetic memory with separate read and write paths
    49.
    发明授权
    Magnetic memory with separate read and write paths 失效
    具有独立读写路径的磁记忆体

    公开(公告)号：US08520432B2

    公开(公告)日：2013-08-27

    申请号：US12974699

    申请日：2010-12-21

    申请人： Yong Lu ,  Hongyue Liu ,  Zheng Gao ,  Insik Jin ,  Dimitar V. Dimitrov

    发明人： Yong Lu ,  Hongyue Liu ,  Zheng Gao ,  Insik Jin ,  Dimitar V. Dimitrov

    IPC分类号： G11C11/14

    CPC分类号： H01L43/02 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

    摘要： Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.

    摘要翻译： 公开了具有分离的读和写路径的磁存储器。 磁存储器单元包括具有第一磁化取向的第一端部，具有第二磁化取向的相对的第二端部和第一端部与第二端部之间的中间部分的铁磁条，所述中间部分具有 自由磁化方向。 第一磁化取向与第二磁化取向相反。 隧道势垒将磁性参考层与形成磁性隧道结的中间部分分开。 位线电耦合到第二端部。 源极线电耦合到第一端部，并且读取线电耦合到磁性隧道结。

    MRAM diode array and access method
    50.
    发明授权
    MRAM diode array and access method 有权
    MRAM二极管阵列和访问方式

    公开(公告)号：US08514605B2

    公开(公告)日：2013-08-20

    申请号：US13611225

    申请日：2012-09-12

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC分类号： G11C5/08 ,  G11C27/00 ,  G11C11/00

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

    摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。