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    Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture
    41.
    发明授权
    Cyclic redundancy checking of a field programmable gate array having an SRAM memory architecture 有权
    具有SRAM存储器架构的现场可编程门阵列的循环冗余校验

    公开(公告)号：US06772387B1

    公开(公告)日：2004-08-03

    申请号：US10351099

    申请日：2003-01-22

    申请人： William C. Plants

    发明人： William C. Plants

    IPC分类号： G11C2900

    CPC分类号： G01R31/318519 ,  G06F11/1004

    摘要： A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises the steps of providing a serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals generated by row column counters, loading data from the serial data stream into the user assignable SRAM in response to address signals generated by row and column counters, loading a seed and signature from the serial data stream into a cyclic redundancy checking circuit, cycling data out of the configuration SRAM and the user assignable SRAM by the row and column counters; performing error checking on the data that has been cycled out of the configuration SRAM and out of the user assignable SRAM by the cyclic redundancy checking circuit, and generating an error signal when an error is detected by the error checking circuit.

    摘要翻译： 用于检测存储在FPGA中的配置SRAM和用户可分配SRAM中的数据中的错误的方法包括以下步骤：将串行数据流从外部源提供到FPGA中，以将数据从串行数据流加载到配置SRAM中以响应于 由行列计数器产生的地址信号，响应于由行和列计数器产生的地址信号将串行数据流中的数据加载到用户可分配SRAM中，将种子和签名从串行数据流加载到循环冗余校验电路中，循环 配置SRAM中的数据和用户可分配的SRAM由行和列计数器; 通过循环冗余校验电路对已从配置SRAM循环出来的数据进行错误检查，并从错误检测电路检测到错误时产生错误信号。

    Field programmable gate array and microcontroller system-on-a-chip
    42.
    发明授权
    Field programmable gate array and microcontroller system-on-a-chip 有权
    现场可编程门阵列和微控制器片上系统

    公开(公告)号：US06751723B1

    公开(公告)日：2004-06-15

    申请号：US09654237

    申请日：2000-09-02

    申请人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

    发明人： Arunangshu Kundu ,  Arnold Goldfein ,  William C. Plants ,  David Hightower

    IPC分类号： G06F1580

    CPC分类号： G06F15/7842 ,  G06F15/7867

    摘要： An system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

    摘要翻译： 片上系统集成电路具有具有逻辑集群，静态随机存取存储器模块和路由资源的现场可编程门阵列核心，具有输入和输出的现场可编程门阵列虚拟组件接口转换器，其中输入被连接 到现场可编程门阵列核心，微控制器，具有输入和输出的微控制器虚拟组件接口转换器，其中输入连接到微控制器，连接到现场可编程门阵列虚拟组件接口转换器的输出的系统总线，以及 到所述微控制器虚拟组件接口转换器的输出，以及微控制器与现场可编程门阵列核心的路由资源之间的直接连接。

    SRAM bus architecture and interconnect to an FPGA
    43.
    发明授权
    SRAM bus architecture and interconnect to an FPGA 失效
    SRAM总线架构和互连到FPGA

    公开(公告)号：US06496887B1

    公开(公告)日：2002-12-17

    申请号：US09512133

    申请日：2000-02-23

    申请人： William C. Plants

    发明人： William C. Plants

    IPC分类号： G06F1300

    CPC分类号： C07K14/475 ,  C07K14/495 ,  H03K19/17736 ,  H03K19/1776

    摘要： An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

    摘要翻译： SRAM总线架构包括直通互连导体。 每个直通互连导体通过包括与三态缓冲器并联连接的传输晶体管的元件连接到FPGA的通用互连架构的路由通道。 传输晶体管和三态缓冲器由配置SRAM位控制。 一些直通互连导体通过可编程元件连接到SRAM块的地址，数据和控制信号线，而其他通过SRAM块进一步连接到SRAM总线架构。

    Methods for errors checking the configuration SRAM and user assignable SRAM data in a field programmable gate array
    44.
    发明授权
    Methods for errors checking the configuration SRAM and user assignable SRAM data in a field programmable gate array 失效
    在现场可编程门阵列中检查配置SRAM和用户可分配SRAM数据的错误方法

    公开(公告)号：US06237124B1

    公开(公告)日：2001-05-22

    申请号：US09039924

    申请日：1998-03-16

    申请人： William C. Plants

    发明人： William C. Plants

    IPC分类号： G11C2900

    CPC分类号： G01R31/318519 ,  G06F11/1004

    摘要： A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises the steps of providing a serial data stream into the FPGA from an external source, loading data from the serial data stream into the configuration SRAM in response to address signals generated by row column counters, loading data from the serial data stream into the user assignable SRAM in response to address signals generated by row and column counters, loading a seed and signature from the serial data stream into a cyclic redundancy checking circuit, cycling data out of the configuration SRAM and the user assignable SRAM by the row and column counters; performing error checking on the data that has been cycled out of the configuration SRAM and out of the user assignable SRAM by the cyclic redundancy checking circuit, and generating an error signal when an error is detected by the error checking circuit.

    摘要翻译： 用于检测存储在FPGA中的配置SRAM和用户可分配SRAM中的数据中的错误的方法包括以下步骤：将串行数据流从外部源提供到FPGA中，以将数据从串行数据流加载到配置SRAM中以响应于 由行列计数器产生的地址信号，响应于由行和列计数器产生的地址信号将串行数据流中的数据加载到用户可分配SRAM中，将种子和签名从串行数据流加载到循环冗余校验电路中，循环 配置SRAM中的数据和用户可分配的SRAM由行和列计数器; 通过循环冗余校验电路对已从配置SRAM循环出来的数据进行错误检查，并从错误检测电路检测到错误时产生错误信号。

    Multiple logic family compatible output driver
    45.
    发明授权
    Multiple logic family compatible output driver 失效
    多逻辑系列兼容输出驱动器

    公开(公告)号：US5952847A

    公开(公告)日：1999-09-14

    申请号：US673701

    申请日：1996-06-25

    申请人： William C. Plants ,  Gregory W. Bakker

    发明人： William C. Plants ,  Gregory W. Bakker

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K19/018521

    摘要： The output buffer circuit according to the present invention is connected to an I/O pad of the integrated circuit. The output buffer circuit includes an output totem pole, a level shifter and enable logic. The output totem pole has a first input connected to the level shifter and a second input connected to the enable logic. The output of the totem pole is connected to an I/O pad. The totem pole includes a pullup transistor connected to 3.3 volt Vcc and a pulldown transistor connected to ground. In a first embodiment of the invention, the pullup transistor in the totem pole is an N-channel MOS transistor, and in a second embodiment of the invention, the pullup transistor in the totem pole is a P-channel MOS transistor formed in an N-well tied to the 5 volt Vcc. In the first embodiment of the present invention, the N-Channel MOS pullup transistor is turned on by a 5 volt signal from the level shifter. In the second embodiment of the present invention, the P-Channel MOS pullup transistor is turned on by a ground level signal from the level shifter. The enable logic drives the output of the totem pole in response to input signals to the enable logic. The inputs to the enable logic are a Data input, a Global enable input and an Output enable input.

    摘要翻译： 根据本发明的输出缓冲器电路连接到集成电路的I / O焊盘。 输出缓冲电路包括输出图腾柱，电平移位器和使能逻辑。 输出图腾柱具有连接到电平移位器的第一输入端和连接到使能逻辑的第二输入端。 图腾柱的输出连接到I / O焊盘。 图腾柱包括连接到3.3伏Vcc的上拉晶体管和连接到地的下拉晶体管。 在本发明的第一实施例中，图腾柱中的上拉晶体管是N沟道MOS晶体管，在本发明的第二实施例中，图腾柱中的上拉晶体管是形成在N沟道MOS晶体管中的P沟道MOS晶体管 - 连接到5伏Vcc。 在本发明的第一实施例中，N沟道MOS上拉晶体管由来自电平移位器的5伏特信号导通。 在本发明的第二实施例中，P沟道MOS上拉晶体管由来自电平移位器的接地电平信号导通。 响应于使能逻辑的输入信号，使能逻辑驱动图腾柱的输出。 使能逻辑的输入是数据输入，全局使能输入和输出使能输入。

    Non-volatile two-transistor programmable logic cell and array layout
    47.
    发明授权
    Non-volatile two-transistor programmable logic cell and array layout 失效
    非易失性双晶体管可编程逻辑单元和阵列布局

    公开(公告)号：US07956404B2

    公开(公告)日：2011-06-07

    申请号：US12370828

    申请日：2009-02-13

    申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

    发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11524 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/7881

    摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

    摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

    NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
    49.
    发明申请
    NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 有权
    非易失性双向晶体管可编程逻辑单元和阵列布局

    公开(公告)号：US20090212343A1

    公开(公告)日：2009-08-27

    申请号：US12417189

    申请日：2009-04-02

    申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

    发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11524 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/7881

    摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

    摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。