公开(公告)号：US07346082B2

公开(公告)日：2008-03-18

申请号：US10361255

申请日：2003-02-10

Applicant: Ali Ghiasi ,  Mohammad Nejad ,  Guangming Yin

Inventor： Ali Ghiasi ,  Mohammad Nejad ,  Guangming Yin

IPC: H04J3/02

CPC classification number: H04J3/047 ,  H04J3/0685

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate and in a natural order. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Abstract translation: 多比特流接口将第一发送数据多路复用集成电路和第二发送数据多路复用集成电路接口。 多比特流接口包括多个发送比特流的接口，每个发送比特流以接口比特率和自然顺序携带相应的比特流。 该接口还包括以对应于接口比特率的一半的频率工作的发送数据时钟。 第一发送数据复用集成电路以第一比特率从通信ASIC接收第一多个发送比特流。 第二发送数据复用集成电路以线路比特率产生单个比特流输出。 所述多个发送比特流的接口被分成第一组和第二组，其中所述第一组在第一组线路上承载，并且所述第二组在第二组线路上承载。 发送数据时钟在相对于第一组线路和第二组线路居中的线路上承载，使得它位于第一组线路组和第二组线路组之间。 接口还可以将第一接收数据解复用集成电路和第二接收数据解复用集成电路接口。

公开(公告)号：US20050248396A1

公开(公告)日：2005-11-10

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

公开(公告)号：US20050218984A1

公开(公告)日：2005-10-06

申请号：US11133723

申请日：2005-05-20

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03D13/00 ,  H03F3/45 ,  H03K19/21 ,  H04L7/033

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract translation: 本发明的方面提供了快速的一级零电流状态异或门。 本发明的实施例提供了第一对差分配置的晶体管和耦合到第一对差分配置的晶体管的电平转换电阻器。 一级零电流状态XOR门还可以包括第二对差分配置的晶体管。 XOR门的核可以耦合到第一对和第二对差分配置的晶体管的输出。

公开(公告)号：US06909332B2

公开(公告)日：2005-06-21

申请号：US10639079

申请日：2003-08-12

Applicant: Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

Inventor： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC: H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H03L7/00

CPC classification number: H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

公开(公告)号：US06754287B2

公开(公告)日：2004-06-22

申请号：US09814196

申请日：2001-03-21

Applicant: Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

Inventor： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

IPC: H04L2720

CPC classification number: H03F3/217 ,  H03F2200/331 ,  H04L27/2046

Abstract: Communications systems, and particularly portable personal communications systems, such as portable phones, are becoming increasingly digital. One area that has remained largely analog, however, is the modulation and RF amplifier circuits. To produce a RF frequency waveform. An output of a class D amplifier is coupled to an integrator to create an analog signal. A resonant circuit shapes an output waveform based on the analog signal to create a sinusoidal RF broadcast signal. The waveform of the class D amplifier may be duty cycle modulated. Digital modulation may occur using a digital sigma delta modulator or a digital programmable divide modulator. Using the digital modulation techniques and class D amplification techniques together allows for broadcast a PSK signal that has been decomposed into amplitude and phase components.

Abstract translation: 通信系统，特别是诸如便携式电话的便携式个人通信系统正在变得越来越数字化。 然而，仍然是模拟的一个领域是调制和RF放大器电路。 产生RF频率波形。 D类放大器的输出耦合到积分器以产生模拟信号。 谐振电路基于模拟信号对输出波形进行整形以产生正弦RF广播信号。 D类放大器的波形可以是占空比调制的。 可以使用数字Σ-Δ调制器或数字可编程分频调制器进行数字调制。 一起使用数字调制技术和D类放大技术可以广播已经分解为幅度和相位分量的PSK信号。

公开(公告)号：US06535735B2

公开(公告)日：2003-03-18

申请号：US09814921

申请日：2001-03-22

Applicant: Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

Inventor： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

IPC: H04Q720

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Modern digital integrated circuits are commonly synchronized in their workings by clock circuits. The clock frequency for a circuit must take into account the propagation delay of signals within the critical path of the circuit. If the clock time is not adequate to allow propagation of signals through the critical path, improper circuit operation may result. The propagation delay is not a constant from circuit to circuit, and even in a single circuit may change due to temperature, power supply voltage and the like. Commonly, this variation is handled by assuming a worse case propagation delay of the critical path, and then designing the clock frequency and minimum power supply voltage of the circuit so that the circuit will function under worst case conditions. However, instead of assuming a worse case propagation delay of the critical path, the propagation delay may be measured in an actual circuit path that has been constructed to be the equivalent to, or slightly worse than, the propagation delay of the critical path. By knowing the actual worst case propagation delay, the circuit may be modified to operate with lower power supply voltages, conserving power and/or to controlling the frequency of the clock, so that the clock may be operated at or near the circuit's actual, not theoretical worst case limit. Such modifications of power supply voltage and/or clock frequency may occur during circuit operation and thus, adapt the circuit to the different operating parameters of each circuit.

公开(公告)号：US07834790B1

公开(公告)日：2010-11-16

申请号：US12206773

申请日：2008-09-09

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03M1/66

CPC classification number: H03M1/002 ,  H03M1/66

Abstract: A communication device includes a communication port that includes a digital to analog converter (DAC) that may be configured to output for transmission an analog signal that corresponds to a digital input such as link data that is to be transmitted on a physical link. The communication port further includes a control unit coupled to the DAC and may be configured to provide a bias current to the DAC during operation. In addition, the control unit may further be configured to reduce the bias current to the DAC dependent upon a mode of operation of the communication port and whether there is data to transmit.

Abstract translation: 通信设备包括通信端口，其包括数模转换器（DAC），其可以被配置为输出用于传输对应于数字输入的模拟信号，例如要在物理链路上传输的链路数据。 通信端口还包括耦合到DAC的控制单元，并且可以被配置为在操作期间向DAC提供偏置电流。 此外，控制单元还可以被配置为根据通信端口的操作模式以及是否存在要发送的数据来减小到DAC的偏置电流。

公开(公告)号：US07449964B2

公开(公告)日：2008-11-11

申请号：US11120738

申请日：2005-05-03

Applicant: Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

Inventor： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC: H03L7/00

CPC classification number: H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract translation: 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US07319351B2

公开(公告)日：2008-01-15

申请号：US11084369

申请日：2005-03-18

Applicant: Bo Zhang ,  Guangming Yin

Inventor： Bo Zhang ,  Guangming Yin

IPC: H03L7/06

CPC classification number: H03H11/265 ,  H03H11/126

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract translation: 延迟电路产生延迟信号。 延迟电路包括具有耦合到周期性输入信号的输入端的延迟锁定环，延迟锁定产生一个或多个延迟周期信号，以及用于控制周期性输入信号和延迟周期信号之间的时间延迟的控制信号。 延迟电路还包括用于产生一个或多个延迟周期信号的受控延迟电路。 受控延迟电路具有用于接收来自延迟锁定环路的延迟周期信号中的至少一个的输入端子和与来自延迟锁存器的控制信号耦合的延迟控制端子，用于控制接收到的延迟的周期性输入信号之间的时间延迟 从延迟锁定环和由受控延迟电路产生的一个或多个延迟周期信号。

公开(公告)号：US07098692B2

公开(公告)日：2006-08-29

申请号：US11078151

申请日：2005-03-11

Applicant: Sridevi R. Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

Inventor： Sridevi R. Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

IPC: H03K19/0175

CPC classification number: H03K19/018585 ,  H04L7/0008

Abstract: An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

Abstract translation: 集成电路包括核心电路和缓冲电路。 缓冲电路包括多个输入缓冲器和多个输出缓冲器，其在单组输入/输出线上服务多个电压域。 这些电压域是可控制的，以满足与各种接口标准一致的多个电压电平。 在一个结构中，核心电路工作在1.2伏特，缓冲电路支持1.2伏接口标准和3.3伏接口标准。