Abstract:
A scanning electron microscope incorporates a multi-pixel solid-state electron detector. The multi-pixel solid-state detector may detect back-scattered and/or secondary electrons. The multi-pixel solid-state detector may incorporate analog-to-digital converters and other circuits. The multi-pixel solid state detector may be capable of approximately determining the energy of incident electrons and/or may contain circuits for processing or analyzing the electron signals. The multi-pixel solid state detector is suitable for high-speed operation such as at a speed of about 100 MHz or higher. The scanning electron microscope may be used for reviewing, inspecting or measuring a sample such as unpatterned semiconductor wafer, a patterned semiconductor wafer, a reticle or a photomask. A method of reviewing or inspecting a sample is also described.
Abstract:
An image sensor for short-wavelength light includes a semiconductor membrane, circuit elements formed on one surface of the semiconductor membrane, and a pure boron layer on the other surface of the semiconductor membrane. An anti-reflection or protective layer is formed on top of the pure boron layer. This image sensor has high efficiency and good stability even under continuous use at high flux for multiple years. The image sensor may be fabricated using CCD (charge coupled device) or CMOS (complementary metal oxide semiconductor) technology. The image sensor may be a two-dimensional area sensor, or a one-dimensional array sensor.
Abstract:
A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.
Abstract:
A pulse multiplier includes a polarizing beam splitter, a wave plate, and a set of multi-surface reflecting components (e.g., one or more etalons and one or more mirrors). The polarizing beam splitter passes input laser pulses through the wave plate to the multi-surface reflecting components, which reflect portions of each input laser pulse back through the wave plate to the polarizing beam splitter. The polarizing beam splitter reflects each reflected portion to form an output of the pulse multiplier. The multi-surface reflecting components are configured such that the output pulses exiting the pulse multiplier have an output repetition pulse frequency rate that is at least double the input repetition pulse frequency.
Abstract:
Inspection of EUV patterned masks, blank masks, and patterned wafers generated by EUV patterned masks requires high magnification and a large field of view at the image plane. An EUV inspection system can include a light source directed to an inspected surface, a detector for detecting light deflected from the inspected surface, and an optic configuration for directing the light from the inspected surface to the detector. In particular, the detector can include a plurality of sensor modules. Additionally, the optic configuration can include a plurality of mirrors that provide magnification of at least 100× within an optical path less than 5 meters long. In one embodiment, the optical path is approximately 2-3 meters long.
Abstract:
A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.
Abstract:
An image sensor for electrons or short-wavelength light includes a semiconductor membrane, circuit elements formed on one surface of the semiconductor membrane, and a pure boron layer on the other surface of the semiconductor membrane. The circuit elements are connected by metal interconnects comprising a refractory metal. An anti-reflection or protective layer may be formed on top of the pure boron layer. This image sensor has high efficiency and good stability even under continuous use at high flux for multiple years. The image sensor may be fabricated using CCD (charge coupled device) or CMOS (complementary metal oxide semiconductor) technology. The image sensor may be a two-dimensional area sensor, or a one-dimensional array sensor.
Abstract:
A multiple-column-per-channel image CCD sensor utilizes a multiple-column-per-channel readout circuit including connected transfer gates that alternately transfer pixel data (charges) from a group of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at multiple times the line clock rate to pass the image charges to the shared output circuit. A symmetrical fork-shaped diffusion is utilized in one embodiment to merge the image charges from the group of related pixel columns. A method of driving the multiple-column-per-channel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the multiple-column-per-channel CCD sensor is also described.
Abstract:
A focusing EBCCD includes a control device positioned between a photocathode and a CCD. The control device has a plurality of holes therein, wherein the plurality of holes are formed perpendicular to a surface of the photocathode, and wherein a pattern of the plurality of holes is aligned with a pattern of pixels in the CCD. Each hole is surrounded by at least one first electrode, which is formed on a surface of the control device facing the photocathode. The control device may include a plurality of ridges between the holes. The control device may be separated from the photocathode by approximately half a shorter dimension of a CCD pixel or less. A plurality of first electrodes may be provided, wherein each first electrode surrounds a given hole and is separated from the given hole by a gap.
Abstract:
A pulse multiplier includes a polarizing beam splitter, a wave plate, and a set of multi-surface reflecting components (e.g., one or more etalons and one or more mirrors). The polarizing beam splitter passes input laser pulses through the wave plate to the multi-surface reflecting components, which reflect portions of each input laser pulse back through the wave plate to the polarizing beam splitter. The polarizing beam splitter reflects each reflected portion to form an output of the pulse multiplier. The multi-surface reflecting components are configured such that the output pulses exiting the pulse multiplier have an output repetition pulse frequency rate that is at least double the input repetition pulse frequency.