公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US5548145A

公开(公告)日：1996-08-20

申请号：US328526

申请日：1994-10-25

申请人： Takeshi Hamamoto ,  Takashi Yamada ,  Yutaka Ishibashi

发明人： Takeshi Hamamoto ,  Takashi Yamada ,  Yutaka Ishibashi

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  H01L27/10829

摘要： A semiconductor memory device comprises a semiconductor substrate having memory cell area, a plurality of trenches selectively formed in the memory cell area aligning in certain intervals and a plurality of memory cell arrays provided in the memory cell area, wherein each of the memory cell arrays comprises a plurality of MOS transistors connected in a serial array and a plurality of capacitors each formed in a corresponding one of the trenches. Each of the transistors has a gate electrode above the substrate with a gate insulating film formed therebetween and source and drain regions formed in the substrate on both sides of the gate electrode. Each of the capacitors includes a charge storage layer formed on an inner wall of each of the trenches and connected integrally to one of the source and drain regions of each of the transistors, a capacitor insulating film formed on the charge storage layer and a capacitor electrode formed on the capacitor insulating film so as to bury each of the trenches and extending to the surface of the substrate, which is formed on the surface of the substrate except for at least formation areas of the transistors.

摘要翻译： 一种半导体存储器件包括具有存储单元区域的半导体衬底，选择性地形成在存储单元区域中以一定间隔对准的多个沟槽和设置在存储单元区域中的多个存储单元阵列，其中每个存储单元阵列包括 以串联阵列连接的多个MOS晶体管和分别形成在对应的一个沟槽中的多个电容器。 每个晶体管在衬底之上具有栅极电极，栅极绝缘膜形成在其间，源极和漏极区域形成在栅电极两侧的衬底中。 每个电容器包括形成在每个沟槽的内壁上并且与每个晶体管的源极和漏极区中的一个一体连接的电荷存储层，形成在电荷存储层上的电容器绝缘膜和电容器电极 形成在电容器绝缘膜上，以埋入每个沟槽并且延伸到形成在基板的表面上的基板的表面，除了晶体管的至少形成区域之外。

公开(公告)号：US5418923A

公开(公告)日：1995-05-23

申请号：US937763

申请日：1992-09-01

申请人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

发明人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory. The circuit is provided with a contention arbitrating circuit for a lower subgroup and a contention arbitrating circuit for a higher subgroup. In the contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for higher subgroup, each coincidence signal simultaneously activates inhibiting signals whose priority levels are lower than the priority level of the coincidence signal. A lower half of coincidence signals are arranged in descending order in the contention arbitrating circuit for a lower subgroup and a higher half of coincidence signals are arranged in ascending order in the contention arbitrating circuit for a higher subgroup. The contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for a higher subgroup are arranged in a triangular array and a complementary triangular array, respectively.

摘要翻译： 当从联想存储器获得符合信号时，编码电路将一致信号所需的时间缩短为根据预定的优先级依次选择和输出之后被转换成地址码。 该电路设置有用于较低子组的竞争仲裁电路和用于较高子组的争用仲裁电路。 在用于较低子组的竞争仲裁电路和较高子组的竞争仲裁电路中，每个符合信号同时激活优先级低于一致信号的优先级的禁止信号。 在下一个子组的竞争仲裁电路中，按照降序排列下半部分的符合信号，并且在较高子组的竞争仲裁电路中按照升序排列较高的一半符号信号。 用于较低子组的争用仲裁电路和用于较高子组的争用仲裁电路分别以三角阵列和互补三角阵列排列。

公开(公告)号：US5388066A

公开(公告)日：1995-02-07

申请号：US084098

申请日：1993-07-01

申请人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G06F17/30 ,  G11C15/00 ,  G11C15/04

CPC分类号： G06F17/30982 ,  G11C15/00 ,  G11C15/04 ,  G11C15/043

摘要： A data storing circuit including memory cells arranged in a plurality of rows and columns and flag cells corresponding to respective rows for storing flag information, the memory cells and the flag cell of the same row constituting one word, is provided. When a retrieval data is externally applied, the data included in the retrieval data is compared with the data of the memory cell, and the flag information stored in the retrieval data is compared with the flag stored in the flag cell. Respective results of comparison are output to a match line. Logical operation circuit carries out logical operation dependent on the result of comparison output to the match line, and writes the logical output to the flag cell of the data storing circuit.

摘要翻译： 一种数据存储电路，其特征在于，具备排列成多个行和列的存储单元以及对应于各行的标志单元，用于存储标志信息，存储单元和构成一个字的同一行的标志单元。 当外部应用检索数据时，将包括在检索数据中的数据与存储单元的数据进行比较，并将存储在检索数据中的标志信息与存储在标志单元中的标志进行比较。 比较结果输出到匹配行。 逻辑运算电路根据比较结果输出到匹配线进行逻辑运算，并将逻辑输出写入数据存储电路的标志单元。

公开(公告)号：US5319589A

公开(公告)日：1994-06-07

申请号：US966921

申请日：1992-10-27

申请人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

发明人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

IPC分类号： G11C15/00 ,  G11C11/4094 ,  G11C15/04 ,  G11C29/04

CPC分类号： G11C11/4094 ,  G11C15/043

摘要： A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.

摘要翻译： 公开了一种用于实现动态内容可寻址存储器的位线控制电路。 位线控制电路包括读取电路12和连接到数据线对DT，/ DT的第一写入电路13，读出放大器14，位线放电电路15，位线充电电路16，传输门电路17 和第二写入电路18.位线控制电路通过位线BLa，/ BLa连接到CAM单元阵列。 可以通过简单的电路配置在简单的定时控制下，在动态关联存储器中所需的诸如写入，读取，刷新和匹配检测等各种操作。

公开(公告)号：US4965767A

公开(公告)日：1990-10-23

申请号：US380428

申请日：1989-07-17

申请人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

发明人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.

摘要翻译： 公开了仅由四个NMOS晶体管组成的相关存储器的存储单元电路。 电路的每个存储单元连接两个位线，字线，用于命令一致检测的匹配设置线和用于传送检测结果的匹配线。 数据信号以每个晶体管3的栅极容量存储。这种简化的存储单元电路有助于关联存储器的更高的集成。

公开(公告)号：US08482044B2

公开(公告)日：2013-07-09

申请号：US12721245

申请日：2010-03-10

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： H01L21/02

CPC分类号： H01L27/11507 ,  H01L27/11504 ,  H01L28/55

摘要： An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.

摘要翻译： 本公开的一个方面，提供了包括铁电电容器和作为存储单元的场效应晶体管的半导体存储器件，所述铁电电容器包括连接到所述一对杂质扩散层中的一个的下电极，形成的位线 在所述下电极下方，其中每个所述存储器单元与所述第一方向上的一侧的相邻存储单元共享位线接触以连接到所述位线，并且所述字线中的三条形成在所述位线接触中 第一个方向

公开(公告)号：US07995369B2

公开(公告)日：2011-08-09

申请号：US12332595

申请日：2008-12-11

申请人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

发明人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

IPC分类号： G11C17/00

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/1203

摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

摘要翻译： 本公开涉及包括位线的半导体存储器件; 字线 布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是半导体层指向字线和位线的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘， 其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

公开(公告)号：US07732271B2

公开(公告)日：2010-06-08

申请号：US12222143

申请日：2008-08-04

申请人： Takeshi Hamamoto ,  Akihiro Nitayama

发明人： Takeshi Hamamoto ,  Akihiro Nitayama

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.

摘要翻译： 根据本发明，提供了一种NAND型半导体存储装置，包括半导体衬底，形成在半导体衬底上的半导体层，在存储晶体管形成区域中选择性地形成在半导体衬底和半导体层之间的埋入绝缘膜， 形成在存储晶体管形成区域的半导体层上的扩散层，扩散层之间的浮体区域，形成在每个浮体区域上的第一绝缘膜，形成在第一绝缘膜上的浮栅，控制电极 形成在浮置栅电极上的第二绝缘膜和连接到分别位于存储晶体管形成区的端部的一对扩散层的接触插塞，其中位于 存储晶体管形成区域的端部连接到半导体 导体基板在接触塞下方。

公开(公告)号：US20080242048A1

公开(公告)日：2008-10-02

申请号：US11559347

申请日：2006-11-13

申请人： Tetsuya Nakai ,  Bong Gyun Ko ,  Takeshi Hamamoto ,  Takashi Yamada

发明人： Tetsuya Nakai ,  Bong Gyun Ko ,  Takeshi Hamamoto ,  Takashi Yamada

IPC分类号： H01L21/762

CPC分类号： H01L21/76243

摘要： To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface.After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

摘要翻译： 为了容易且准确地将用作SOI区域的基板表面与用作主体区域的基板表面冲洗，形成掩埋氧化膜，并且防止氧化膜暴露在基板表面上。 在由单晶硅构成的基板12的表面上部分地形成掩模氧化膜23之后，通过掩模氧化膜将氧离子16注入基板的表面，并将基板退火以形成掩埋氧化膜13 在基板内。 还包括形成预定深度的凹部12c的步骤，该预定深度凹部12c比作为其上形成有掩模氧化膜的基板表面12b更深地形成在作为SOI区域的基板表面12a上的掩模氧化膜， 在形成掩模氧化膜的步骤和注入氧离子的步骤之间作为其上没有形成掩模氧化物膜的SOI区域的衬底表面12a上的氧化物膜21。