公开(公告)号：US09281278B2

公开(公告)日：2016-03-08

申请号：US13286224

申请日：2011-11-01

申请人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

发明人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

摘要翻译： 提出了一种形成半导体器件的方法。 提供了在其上形成有介电层的基板。 在介电层上形成第一上蚀刻停止层。 第一上蚀刻停止层包括第一电介质材料。 将电介质层和第一上蚀刻停止层图案化以形成互连开口。 互连开口填充有导电材料以形成互连。 互连和第一上蚀刻停止层具有共面的顶表面。 第二上蚀刻停止层形成在共面顶表面上。 第二上蚀刻停止层包括与第一材料具有足够粘合力以减少导电材料扩散的第二材料。

公开(公告)号：US08809183B2

公开(公告)日：2014-08-19

申请号：US12887010

申请日：2010-09-21

申请人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Lawrence A. Clevenger ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76862 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

摘要翻译： 选择性导电盖通过对金属互连结构的暴露的下面的电介质表面可选择的化学镀层沉积在金属线的暴露的金属表面上。 介电材料层沉积在选择性导电盖和暴露的下面的介质层上，而不需要预清洗。 介电材料层被平坦化以形成与选择性导电帽的最顶面共面的水平平面。 执行预清洁，并且在选择性导电盖和介电材料层的平坦化表面上沉积电介质盖层。 由于包括由预清洗层损坏的表面的界面垂直偏离金属线的最上表面，所以金属线中的金属沿着界面的电迁移减少或消除。

公开(公告)号：US08772941B2

公开(公告)日：2014-07-08

申请号：US12206314

申请日：2008-09-08

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L23/522

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

公开(公告)号：US08614115B2

公开(公告)日：2013-12-24

申请号：US12916236

申请日：2010-10-29

申请人： Lawrence A. Clevenger ,  Harold J. Hovel ,  Rainer Klaus Krause ,  Kevin S. Petrarca ,  Gerd Pfeiffer ,  Kevin M. Prettyman ,  Carl Radens ,  Brian C. Sapp

发明人： Lawrence A. Clevenger ,  Harold J. Hovel ,  Rainer Klaus Krause ,  Kevin S. Petrarca ,  Gerd Pfeiffer ,  Kevin M. Prettyman ,  Carl Radens ,  Brian C. Sapp

IPC分类号： H01L21/00 ,  H01L31/18

CPC分类号： H01L31/022425 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.

摘要翻译： 光伏太阳能电池器件的制造方法包括以下。 形成具有第一掺杂密度的p-n结。 通过引入第二掺杂密度以形成用于双发射器应用的高掺杂区域来增强p-n结的形成。 高掺杂区域由与p-n结的形成集成的掩模工艺限定，产生高掺杂区域的掩模图案。 根据高掺杂区域的掩模图案发生高掺杂区域的金属化。

公开(公告)号：US08535970B2

公开(公告)日：2013-09-17

申请号：US13154140

申请日：2011-06-06

申请人： Ranier Krauser ,  Lawrence A. Clevenger ,  Kevin Prettyman ,  Brian Christopher Sapp ,  Kevin S. Petrarca ,  Harold John Hovel ,  Gerd Pfeiffer ,  Zhengwen Li ,  Carl John Radens

发明人： Ranier Krauser ,  Lawrence A. Clevenger ,  Kevin Prettyman ,  Brian Christopher Sapp ,  Kevin S. Petrarca ,  Harold John Hovel ,  Gerd Pfeiffer ,  Zhengwen Li ,  Carl John Radens

IPC分类号： H01L21/00

CPC分类号： H01L31/1804 ,  H01L31/02167 ,  H01L31/022425 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521

摘要： The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.

摘要翻译： 本发明涉及一种光伏太阳能电池（100）的制造方法，包括：在光伏太阳能电池（100）的后侧（18）上提供高掺杂区域（20），提供位于所述光伏太阳能电池（100）上的局部金属触点（30） 提供覆盖所述触头（30）之间的表面（52）的钝化层（50），其中触点（30）保持基本上不含钝化层（50），并沉积金属层（50） 32）用于背面场。

公开(公告)号：US20120313144A1

公开(公告)日：2012-12-13

申请号：US13494965

申请日：2012-06-12

申请人： John H. ZHANG ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

发明人： John H. ZHANG ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/7781

摘要： A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

摘要翻译： 一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。 沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

公开(公告)号：US20120126937A1

公开(公告)日：2012-05-24

申请号：US13296242

申请日：2011-11-15

申请人： Lawrence A. Clevenger ,  Rainer K. Krause ,  Kevin S. Petrarca ,  Carl J. Radens ,  Brian C. Sapp

发明人： Lawrence A. Clevenger ,  Rainer K. Krause ,  Kevin S. Petrarca ,  Carl J. Radens ,  Brian C. Sapp

IPC分类号： G08B29/00

CPC分类号： G08B13/14 ,  G06Q10/087

摘要： Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.

摘要翻译： 用于控制电器的资产管理包括密码单元和嵌入在器具中的设备单元。 键码单元位于受保护的环境中，与资产管理区域有关。 设备单元可以存储设备标识码。 键码单元和设备单元可以是通信接触的，由此设备单元向键码单元发送定位坐标，并且其中设备单元适于经由锁定单元锁定设备，响应于锁定信号，设备 如果设备移动到资产管理区域外，则单元从密钥单元接收。

公开(公告)号：US08143166B2

公开(公告)日：2012-03-27

申请号：US12046151

申请日：2008-03-11

申请人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

发明人： Feng Zhao ,  Wu Ping Liu ,  John Sudijono ,  Laertis Economikos ,  Lawrence A. Clevenger

IPC分类号： H01L21/461

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

摘要翻译： 在半导体器件制造工艺中的抛光工艺使用其中在抛光组合物内产生气相的抛光组合物。 在抛光过程中，气相通过抛光期间的化学和磨蚀作用动态地响应经历去除的材料的表面轮廓的变化。 惰性气泡密度在被抛光的基底的表面区域附近动态增加，这些表面区域易于发生凹陷和侵蚀。 增加的惰性气泡密度用于降低相对于基底的其它区域的抛光去除速率。 抛光组合物中气相的动态作用用于选择性地降低局部抛光去除速率，使得获得与抛光过程中图案密度的影响无关的均匀光滑和平坦的抛光表面。

公开(公告)号：US08053361B2

公开(公告)日：2011-11-08

申请号：US12203924

申请日：2008-09-04

申请人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

发明人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

IPC分类号： H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

摘要翻译： 提出了一种形成半导体器件的方法。 提供了在其上形成有介电层的基板。 在介电层上形成第一上蚀刻停止层。 第一上蚀刻停止层包括第一电介质材料。 将电介质层和第一上蚀刻停止层图案化以形成互连开口。 互连开口填充有导电材料以形成互连。 互连和第一上蚀刻停止层具有共面的顶表面。 第二上蚀刻停止层形成在共面顶表面上。 第二上蚀刻停止层包括与第一材料具有足够粘合力以减少导电材料扩散的第二材料。

公开(公告)号：US08026166B2

公开(公告)日：2011-09-27

申请号：US12190131

申请日：2008-08-12

申请人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-sang Oh

发明人： Griselda Bonilla ,  Tien Cheng ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Chao-Kun Hu ,  Roger A. Quon ,  Zhiguo Sun ,  Wei-tsui Tseng ,  Yiheng Xu ,  Yun Wang ,  Hyeok-sang Oh

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.

摘要翻译： 提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。 在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小的N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。