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84 条记录 (耗时 0.022 秒)

    Method of forming a planar polymer transistor using substrate bonding techniques
    41.
    发明授权
    Method of forming a planar polymer transistor using substrate bonding techniques 失效
    使用基板接合技术形成平面聚合物晶体管的方法

    公开(公告)号：US06620657B2

    公开(公告)日：2003-09-16

    申请号：US10052151

    申请日：2002-01-15

    申请人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

    发明人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

    IPC分类号： H01L2100

    CPC分类号： H01L51/0001 ,  H01L51/0024 ,  H01L51/0516 ,  H01L51/0541 ,  H01L51/0545

    摘要： A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistors made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

    摘要翻译： 通过使用第一平面载体来形成包括栅极，源极，漏极和主体元件的器件的第一部分来形成完全平坦化的聚合物薄膜晶体管的结构和方法。 优选地，由所有有机材料制成的薄膜晶体管。 栅极电介质可以是高k聚合物，以提高器件性能。 然后，部分完成的装置结构被颠倒翻转并转移到第二平面载体。 然后施加一层蜡或光敏有机材料，并且可以用作临时胶。 然后通过蚀刻工艺限定该装置，包括其身体区域。 与器件的接触通过导电材料沉积和化学机械抛光形成。

    Method and structure for providing improved thermal conduction for silicon semiconductor devices
    43.
    发明授权
    Method and structure for providing improved thermal conduction for silicon semiconductor devices 有权

    公开(公告)号：US06573565B2

    公开(公告)日：2003-06-03

    申请号：US09362399

    申请日：1999-07-28

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsomg-Dih Yuan

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsomg-Dih Yuan

    IPC分类号： H01L2362

    CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

    Refresh control circuit for low-power SRAM applications
    44.
    发明授权
    Refresh control circuit for low-power SRAM applications 有权
    刷新控制电路，用于低功耗SRAM应用

    公开(公告)号：US06434076B1

    公开(公告)日：2002-08-13

    申请号：US09766799

    申请日：2001-01-22

    申请人： John E. Andersen ,  Louis L. Hsu ,  Stephen Kosonocky ,  Li-Kong Wang

    发明人： John E. Andersen ,  Louis L. Hsu ,  Stephen Kosonocky ,  Li-Kong Wang

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C11/406

    摘要： A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.

    摘要翻译： 一种用于SRAM系统的电源管理电路，包括一个或多个隔离存储器阵列，并且在主动操作模式期间实现包括与每个存储器阵列相关联的本地电源的电源和连接到本地电源的外部电源。 电源管理电路包括：开关机构，用于在低功率操作模式期间断开外部电源到每个本地电源; 以及通过在低功率模式期间选择性地将外部电源连接到各个本地电源来实现存储器阵列刷新操作的刷新定时电路。 在低功率模式期间，刷新电路有意地使本地电源浮动并允许其在存储器阵列刷新操作之前漂移到较低的预定电压电平。

    System and method for preventing noise cross contamination between embedded DRAM and system chip
    45.
    发明授权
    System and method for preventing noise cross contamination between embedded DRAM and system chip 失效
    嵌入式DRAM与系统芯片之间的噪声交叉污染防止系统和方法

    公开(公告)号：US06349067B1

    公开(公告)日：2002-02-19

    申请号：US09772461

    申请日：2001-01-30

    申请人： Louis L. Hsu ,  Richard M. Parent ,  Li-Kong Wang ,  Matthew R. Wordeman

    发明人： Louis L. Hsu ,  Richard M. Parent ,  Li-Kong Wang ,  Matthew R. Wordeman

    IPC分类号： G11C702

    CPC分类号： G11C7/02 ,  G11C7/18 ,  G11C2207/104 ,  H01L21/761 ,  H01L21/823481 ,  H01L27/10897

    摘要： A complete solution to block noise from eDRAM macro to the analog core, and vice verse, in a system-on-chip IC design. Specifically, there is provided a first isolated triple well structure formed in the IC for reducing noise component resulting from operative elements of a DC generator circuit fabricated therein; and, a second isolated triple well structure formed in the IC for reducing noise component resulting from operative elements of a noise sense amplifier bank and DRAM arrays fabricated therein. A power supply source is provided for supplying power to each DC generator circuit, noise sense amplifier bank and DRAM array; as is a power bus for providing power and a separate power bus for providing a ground to each of the DC generator circuit, and the noise sense amplifier circuit and DRAM array components. In this manner, noise contamination with noise sensitive devices in said IC is reduced and, further noise contamination of the DRAM array as sourced from the IC is reduced.

    摘要翻译： 一种完整的解决方案，可以将eDRAM宏的噪声阻挡到模拟核心，而在片上系统集成电路设计中也是如此。 具体地，提供了一种形成在IC中的用于减少由其中制造的直流发电机电路的操作元件产生的噪声分量的第一隔离三重阱结构; 以及形成在IC中的用于降低噪声检测放大器组的操作元件和其中制造的DRAM阵列产生的噪声分量的第二隔离三重阱结构。 提供电源，用于向每个DC发生器电路，噪声检测放大器组和DRAM阵列供电; 用于提供电力的电源总线和用于向每个DC发电机电路以及噪声检测放大器电路和DRAM阵列组件提供接地的单独的电源总线。 以这种方式，减少了所述IC中噪声敏感器件的噪声污染，并且降低了来自IC的DRAM阵列的进一步的噪声污染。

    Segmented content addressable memory architecture for improved cycle time and reduced power consumption
    46.
    发明授权
    Segmented content addressable memory architecture for improved cycle time and reduced power consumption 有权
    分段内容可寻址内存架构，可提高周期时间并降低功耗

    公开(公告)号：US07355872B2

    公开(公告)日：2008-04-08

    申请号：US10673801

    申请日：2003-09-29

    申请人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

    发明人： Louis L. Hsu ,  Brian L. Ji ,  Li-Kong Wang

    IPC分类号： G11C15/04

    CPC分类号： G11C15/04

    摘要： A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the plurality of CAM cells includes a wordline, a matchline and a sinkline, the wordline being shared by all of the cells in the same row, the matchline and sinkline being shared by all of the cells in the same segment; and a corresponding method of searching within a CAM system includes providing an input word to the CAM system, comparing a portion of the input word in a segment of the CAM system, and propagating a mismatch to obviate the need for comparison in other segments of the CAM system.

    摘要翻译： 内容可寻址存储器（“CAM”）系统包括以阵列排列的多个段，其中多个段中的每个段包括多个CAM单元，多个CAM单元中的每一个包括字线，匹配线和下沉线 ，该字线由同一行中的所有单元共享，匹配线和汇线由同一段中的所有单元共享; 并且相应的在CAM系统内搜索的方法包括向CAM系统提供输入字，比较CAM系统的片段中的输入字的一部分，并且传播不匹配，以避免在 CAM系统。