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243 条记录 (耗时 0.029 秒)

    Etch process for aligning a capacitor structure and an adjacent contact corridor
    41.
    发明授权
    Etch process for aligning a capacitor structure and an adjacent contact corridor 有权
    用于对齐电容器结构和相邻触点走廊的蚀刻工艺

    公开(公告)号：US06274423B1

    公开(公告)日：2001-08-14

    申请号：US09236761

    申请日：1999-01-25

    申请人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    发明人： Kirk D. Prall ,  Pierre Fazan ,  Trung Doan ,  Tyler Lowrey

    IPC分类号： H01L218242

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.

    摘要翻译： 用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。 该蚀刻工艺在形成于半导体衬底上的电容器结构中实施。电容器结构包括第一导体，第一导体上的电介质层和介电层上的第二导体。 第二导体具有横向邻近并远离第一导体延伸的水平区域。 蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。 或者，使用单个各向同性蚀刻去除第二导体的水平区域。

    Method of forming a resistor and integrated circuitry having a resistor construction
    43.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 有权
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US06130137A

    公开(公告)日：2000-10-10

    申请号：US170792

    申请日：1998-10-13

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L21/20

    CPC分类号： H01L28/20

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

    Method of forming a resistor and integrated circuitry having a resistor construction
    47.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 失效
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US5668037A

    公开(公告)日：1997-09-16

    申请号：US679705

    申请日：1996-07-11

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L27/08 ,  H01L21/70

    CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802 ,  Y10S148/136

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

    Method for forming and tailoring the electrical characteristics of semiconductor devices
    48.
    发明授权
    Method for forming and tailoring the electrical characteristics of semiconductor devices 失效
    用于形成和定制半导体器件的电特性的方法

    公开(公告)号：US5405788A

    公开(公告)日：1995-04-11

    申请号：US66835

    申请日：1993-05-24

    申请人： Monte Manning ,  Charles Dennison ,  Howard Rhodes ,  Tyler Lowrey

    发明人： Monte Manning ,  Charles Dennison ,  Howard Rhodes ,  Tyler Lowrey

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8244 ,  H01L21/265

    CPC分类号： H01L29/66659 ,  H01L21/823412 ,  H01L27/11

    摘要： A method for forming semiconductor devices includes a low energy implant for tailoring the electrical characteristics of the semiconductor devices. Using the low energy implant, narrow width devices such as access transistors in an SRAM cell, can be fabricated with a low threshold voltage (Vt). The low energy implant is performed on the active areas of a silicon substrate following field isolation and field implant. For an n-conductivity access transistor, the low energy dopant can be an n-type dopant such as phosphorus, arsenic or antimony.

    摘要翻译： 用于形成半导体器件的方法包括用于调整半导体器件的电特性的低能量注入。 使用低能量注入，可以以低阈值电压（Vt）制造诸如SRAM单元中的存取晶体管的窄宽度器件。 在场隔离和场植入之后，在硅衬底的有源区域上执行低能量注入。 对于n导电性存取晶体管，低能掺杂剂可以是n型掺杂剂，例如磷，砷或锑。

    Method of fabricating phase shifting reticles using ion implantation
    49.
    发明授权
    Method of fabricating phase shifting reticles using ion implantation 失效
    使用离子注入制造相移标线的方法

    公开(公告)号：US5217830A

    公开(公告)日：1993-06-08

    申请号：US676939

    申请日：1991-03-26

    申请人： Tyler Lowrey

    发明人： Tyler Lowrey

    IPC分类号： G03F1/30

    CPC分类号： G03F1/30

    摘要： A method of fabricating a phase shifting reticle that can be used as a mask in photolithographic processes such as semiconductor wafer patterning. A transparent quartz substrate is first coated with a patterned resist. The quartz substrate is then subjected to high voltage ion bombardment to produce a pattern of ion implant areas on the substrate. The ion implantation is closely controlled to produce areas on the substrate having an index of refraction different than the quartz substrate and selected to achieve a 180.degree. phase shift. An opaque film is then deposited over the substrate and patterned with openings. This produces a repetitive pattern of alternating light transmission openings and phase shifters having opaque light blockers on either side.

    摘要翻译： 一种制造可用作诸如半导体晶片图案化的光刻工艺中的掩模的相移掩模版的方法。 首先用图案化的抗蚀剂涂覆透明石英基板。 然后对石英衬底进行高压离子轰击，以在衬底上产生离子注入区域的图案。 密切地控制离子注入以产生具有不同于石英衬底的折射率的衬底上的区域，并且被选择以实现180°的相移。 然后将不透明膜沉积在基底上并用开口图案化。 这产生交替的光传输开口的重复图案和在任一侧上具有不透明光阻挡器的移相器。