公开(公告)号：US10911229B2

公开(公告)日：2021-02-02

申请号：US15864445

申请日：2018-01-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Chin-Hung Chang

IPC: G06F11/30 ,  H04L9/08 ,  H04L9/32 ,  G06F12/14 ,  G11C7/24 ,  G09C1/00 ,  G11C16/22 ,  G06F12/02 ,  H03K19/003 ,  G11C7/10 ,  G11C8/20 ,  G11C16/04

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

公开(公告)号：US09672881B2

公开(公告)日：2017-06-06

申请号：US14719678

申请日：2015-05-22

Applicant: Macronix International Co., Ltd.

Inventor： Ken-Hui Chen ,  Kuen Long Chang ,  Chin-Hung Chang

IPC: G11C7/22 ,  G06F13/16

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/222

Abstract: A memory device includes a variable strobe interface configured to select one of a data queue strobe signal or a system clock signal to signal initiation of data receipt at the memory device.

公开(公告)号：US09368220B2

公开(公告)日：2016-06-14

申请号：US14451166

申请日：2014-08-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo ,  Chin-Hung Chang ,  Chang-Ting Chen

IPC: G11C16/16 ,  G11C16/14 ,  G11C29/34 ,  G11C16/04 ,  G11C29/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/14 ,  G11C29/34 ,  G11C2029/2602

Abstract: A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

Abstract translation: 非易失性存储器阵列具有不同持续时间的多个擦除过程。 可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

公开(公告)号：US20150023120A1

公开(公告)日：2015-01-22

申请号：US14506768

申请日：2014-10-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Su-Chueh Lo ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/1048 ,  G11C7/06 ,  G11C7/08 ,  G11C7/106 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

Abstract: A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

Abstract translation: 提供了存储器件的读取操作。 选择的字线，第一和第二全局位线组和所选择的第一位线组被预先充电。 流过所选字线的第一单元电流，产生第一和所选择的第一位线组。 产生流过第二全局位线组的第一参考电流。 基于第一单元电流和第一参考电流来读取前​​半页数据。 所选择的字线，第一和第二全局位线组保持预充电。