公开(公告)号：US10379926B2

公开(公告)日：2019-08-13

申请号：US14596768

申请日：2015-01-14

Applicant: Macronix International Co., Ltd.

Inventor： Kuen Long Chang ,  Ken Hui Chen ,  Su Chueh Lo ,  Chia-Feng Cheng

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/02

Abstract: A method for monitoring data error status of a memory device includes generating, by a memory controller, a data status indication code indicating error status of a data chunk transmitted by the memory controller and outputting, by the memory controller, the data status indication code to a user interface.

公开(公告)号：US09514088B2

公开(公告)日：2016-12-06

申请号：US14619336

申请日：2015-02-11

Applicant: Macronix International Co., Ltd.

Inventor： Ken Hui Chen ,  Kuen Long Chang ,  Yu Chen Wang

IPC: H04L27/10 ,  G06F13/42 ,  G06F13/16 ,  H04L25/49 ,  G11B20/14 ,  H03M5/12

CPC classification number: G06F13/4291 ,  G06F13/1689 ,  G06F13/4234 ,  G11B20/1419 ,  H03M5/12 ,  H04L25/4904

Abstract: A method for command processing in a memory controller includes receiving a serial input signal including a series of binary digits, capturing the binary digits at ones of odd locations or even locations of the serial input signal to form a first sub-series, capturing the binary digits at other ones of the odd locations or the even locations of the serial input signal to form a second sub-series, comparing the first and second sub-series, and performing a command represented by the first sub-series, if the first and second sub-series are complementary to each other.

Abstract translation: 一种用于在存储器控制器中进行命令处理的方法，包括接收包括一系列二进制数字的串行输入信号，捕获串行输入信号的奇数位或偶数位置处的二进制数位以形成第一子序列，捕获二进制数 在串行输入信号的奇数位置或偶数位置的其他位置处的数字，以形成第二子序列，比较第一和第二子序列，并执行由第一子序列表示的命令，如果第一和第 第二个子系列互为补充。

公开(公告)号：US10409735B2

公开(公告)日：2019-09-10

申请号：US15133864

申请日：2016-04-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen Long Chang ,  Yu Chen Wang ,  Ken Hui Chen

IPC: G06F13/14 ,  G06F13/12 ,  G06F13/364 ,  G06F12/02 ,  G06F13/42 ,  G06F13/40

Abstract: An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and transmit a third bit indicative of a mode of operation of the memory device.

公开(公告)号：US09852811B2

公开(公告)日：2017-12-26

申请号：US14851377

申请日：2015-09-11

Applicant: Macronix International Co., Ltd.

Inventor： Kuen Long Chang ,  Ken Hui Chen ,  Su Chueh Lo ,  Chia-Feng Cheng

IPC: G06F11/00 ,  G11C29/52 ,  G06F11/10 ,  G11C29/02 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1004 ,  G11C29/02 ,  G11C2029/0411

Abstract: In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified.

公开(公告)号：US09519539B2

公开(公告)日：2016-12-13

申请号：US14612369

申请日：2015-02-03

Applicant: Macronix International Co., Ltd.

Inventor： Kuen Long Chang ,  Ken Hui Chen ,  Su Chueh Lo ,  Chia-Feng Cheng

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653

Abstract: A method for outputting data error status of a memory device includes generating data status indication codes indicating error status of data chunks transmitted by a memory controller, and combining the data status indication codes with corresponding data chunks to generate an output signal, and outputting the output signal to a data bus pin.

Abstract translation: 一种用于输出存储器件的数据错误状态的方法，包括产生指示由存储器控制器发送的数据块的错误状态的数据状态指示代码，并将数据状态指示代码与相应的数据块组合以产生输出信号，并输出输出 信号到数据总线引脚。

公开(公告)号：US09672881B2

公开(公告)日：2017-06-06

申请号：US14719678

申请日：2015-05-22

Applicant: Macronix International Co., Ltd.

Inventor： Ken-Hui Chen ,  Kuen Long Chang ,  Chin-Hung Chang

IPC: G11C7/22 ,  G06F13/16

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G11C7/222

Abstract: A memory device includes a variable strobe interface configured to select one of a data queue strobe signal or a system clock signal to signal initiation of data receipt at the memory device.