公开(公告)号：US20230291693A1

公开(公告)日：2023-09-14

申请号：US17588295

申请日：2022-01-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Saar Tarnopolsky ,  Avi Urman ,  Dotan David Levi ,  Elena Agostini

IPC: H04L47/2441 ,  H04L69/22

CPC classification number: H04L47/2441 ,  H04L69/22

Abstract: In one embodiments, data communication system include a communication apparatus, which is configured to receive data from different user equipment devices a schedule of time periods, and packetize the data from respective ones of the user equipment devices for respective ones of the time periods into packets, a memory including a plurality of buffers, and a network interface controller configured to receive the packets from the communication apparatus, and scatter respective portions of the data belonging to respective groups of successive ones of the time periods to the buffers, responsively to a static set of steering rules, and timing information of respective ones of the packets, and wherein each respective portion of the data is scattered to the buffers a same scatter pattern.

公开(公告)号：US20230269684A1

公开(公告)日：2023-08-24

申请号：US17675548

申请日：2022-02-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Wojciech Wasko ,  Dotan David Levi ,  Natan Manevich ,  Timothy James Martin

IPC: H04W56/00

CPC classification number: H04W56/0045

Abstract: A network adapter comprises an output that couples to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to be synchronized with a second clock that is external to the CPU and the network adapter, and circuitry coupled to the first clock. The circuitry is configured to generate, using the synchronized first clock, a tick at a time offset from a timeslot of a radio schedule for a radio unit and send the tick to the output.

公开(公告)号：US20230239068A1

公开(公告)日：2023-07-27

申请号：US17665600

申请日：2022-02-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ioannis (Giannis) Patronas ,  Wojciech Wasko ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Elad Mentovich

IPC: H04J14/08 ,  H04J14/02

CPC classification number: H04J14/08 ,  H04J14/0212 ,  H04J14/0267

Abstract: A network adapter includes a host interface and a scheduler. The host interface is configured to receive, from one or more hosts, packets for transmission to respective destinations over a network. The scheduler is configured to synchronize to a time-division schedule that is employed in the network, the time-division schedule specifying (i) multiple time-slots and (ii) multiple respective groups of the destinations that are reachable during the time-slots, and, based on the time-division schedule, to schedule transmission times of the packets to the network on time-slots during which the respective destinations of the packets are reachable.

公开(公告)号：US20230236624A1

公开(公告)日：2023-07-27

申请号：US17582058

申请日：2022-01-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Natan Manevich ,  Bar Shapira

IPC: G06F1/14 ,  H04J3/06 ,  G06F1/12

CPC classification number: G06F1/14 ,  H04J3/0697 ,  H04J3/0682 ,  H04J3/0661 ,  H04J3/0679 ,  G06F1/12

Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.

公开(公告)号：US20230163869A1

公开(公告)日：2023-05-25

申请号：US17534776

申请日：2021-11-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Bar Shapira ,  Ariel Almog ,  Dotan David Levi ,  Natan Manevich ,  Thomas Kernen ,  Liron Mula

IPC: H04J3/06

CPC classification number: H04J3/0638

Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.

公开(公告)号：US11637557B2

公开(公告)日：2023-04-25

申请号：US17670540

申请日：2022-02-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ran Ravid ,  Aviv Berg ,  Lavi Koch ,  Chen Gaist ,  Dotan David Levi

IPC: H03L7/08 ,  G06F1/12 ,  H04L7/033 ,  H03L7/099

Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.

公开(公告)号：US20220416925A1

公开(公告)日：2022-12-29

申请号：US17359667

申请日：2021-06-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

IPC: H04J3/06

Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

公开(公告)号：US20220385598A1

公开(公告)日：2022-12-01

申请号：US17824954

申请日：2022-05-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Boris Pismenny ,  Dotan David Levi ,  Gal Yefet

IPC: H04L49/552 ,  H04L49/90 ,  H04L49/9057 ,  H04W28/04 ,  H04L49/901 ,  H04L65/61 ,  H04L65/65

Abstract: A method for communication includes mapping transport sequence numbers in headers of data packets received from a network to respective buffers in a memory of a host computer. At least a part of the data from payloads of the received data packets is written directly to the respective buffers.

公开(公告)号：US11476928B2

公开(公告)日：2022-10-18

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04L49/351 ,  H04L49/90 ,  H04W72/04 ,  H04W74/08

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.

公开(公告)号：US20220283964A1

公开(公告)日：2022-09-08

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/1045 ,  G06F15/173 ,  G06F9/46 ,  G06F9/455

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.