公开(公告)号：US09546431B2

公开(公告)日：2017-01-17

申请号：US14185613

申请日：2014-02-20

Applicant: Microfabrica Inc.

Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Kieun Kim ,  Qui T. Le ,  Gang Zhang ,  Uri Frodis ,  Dale S. McPherson ,  Dennis R. Smalley

IPC: C25D5/02 ,  C25D1/00 ,  C23C18/16 ,  B81C1/00

CPC classification number: C25D5/022 ,  B81C1/00126 ,  B81C2201/0109 ,  B81C2201/019 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  Y10T156/11 ,  Y10T156/19

Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.

Abstract translation: 本发明的一些实施例涉及在电介质或部分电介质基底上建立单层或多层结构的技术。 某些实施方案将种子层材料直接沉积到基底材料上，而其它实施例使用中间粘合层材料。 一些实施例使用不同种子层材料和/或用于牺牲和结构导电建筑材料的粘合层材料。 一些实施例将种子层和/或粘合层材料应用于有选择性的方式，而其它实施例以毯子的方式应用材料。 一些实施例通过平面化操作去除外来沉积物（例如沉积到不想要形成层的一部分的区域），而其他实施例通过蚀刻操作去除外来材料。 其它实施方案涉及使用至少一种导电结构材料，至少一种导电牺牲材料和至少一种电介质材料形成的多层中尺度或微结构结构的电化学制造。 在一些实施方案中，电介质材料是可UV固化的光聚合物。

公开(公告)号：US09441661B2

公开(公告)日：2016-09-13

申请号：US14054139

申请日：2013-10-15

Applicant: Microfabrica Inc.

Inventor： Uri Frodis ,  Adam L. Cohen ,  Christopher R. Folk

IPC: F16B35/04 ,  F16B33/02

CPC classification number: F16B33/02

Abstract: Embodiments of the invention provide threaded elements alone, in mating pairs, or in conjunction with other elements. Embodiments of the invention also provide for design and fabrication of such threaded elements without violating minimum feature size design rules or causing other interference issues that may result from the fabrication of such thread elements using a multi-layer multi-material electrochemical fabrication process.

公开(公告)号：US20160200073A1

公开(公告)日：2016-07-14

申请号：US15076490

申请日：2016-03-21

Applicant: Microfabrica Inc.

Inventor： Gregory P. Schmitz ,  Michael S. Lockard ,  Ming-Ting Wu ,  Eric C. Miller ,  Adam L. Cohen

IPC: B32B15/01 ,  C25D5/48 ,  C25D5/02

CPC classification number: C25D1/003 ,  B32B15/01 ,  B33Y10/00 ,  B33Y40/00 ,  B33Y70/00 ,  B33Y80/00 ,  C25D1/08 ,  C25D5/022 ,  C25D5/48 ,  C25D7/005

Abstract: A counterfeiting deterrent device according to one implementation of the disclosure includes a plurality of layers formed by an additive process. Each of the layers may have a thickness of less than 100 microns. At least one of the layers has a series of indentations formed in an outer edge of the layer such that the indentations can be observed to verify that the device originated from a predetermined source. According to another implementation, a counterfeiting deterrent device includes at least one raised layer having outer edges in the shape of a logo. A light source is configured and arranged to shine a light through a slit in a substrate layer of the device and past an intermediate layer to light up the outer edge of the raised layer. The layers of the device are formed by an additive process and have a thickness of less than 100 microns each.

Abstract translation: 根据本公开的一个实施方式的防伪装置包括通过添加过程形成的多个层。 每个层可以具有小于100微米的厚度。 层中的至少一个具有形成在层的外边缘中的一系列凹痕，使得可以观察到凹痕以验证装置源自预定源。 根据另一个实施方案，一种防伪装置包括至少一个具有标志形状的外边缘的凸起层。 光源被配置和布置成将光照射穿过设备的基底层中的狭缝并且经过中间层以照亮凸起层的外边缘。 装置的层通过添加工艺形成，并且具有小于每个100微米的厚度。

公开(公告)号：US20140216941A1

公开(公告)日：2014-08-07

申请号：US14185530

申请日：2014-02-20

Applicant: Microfabrica Inc.

Inventor： Gang Zhang ,  Adam L. Cohen ,  Michael S. Lockard ,  Ananda H. Kumar ,  Ezekiel J.J. Kruglick ,  Kieun Kim

IPC: C25D5/50 ,  C25D5/02

CPC classification number: C25D5/50 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D5/12 ,  C25D5/14 ,  C25D5/18 ,  C25D5/34 ,  C25D5/40 ,  C25D5/48 ,  H01L21/2885 ,  H01L21/76879 ,  H05K3/241 ,  H05K3/243

Abstract: Multi-layer microscale or mesoscale structures are fabricated with adhered layers (e.g. layers that are bonded together upon deposition of successive layers to previous layers) and are then subjected to a heat treatment operation that enhances the interlayer adhesion significantly. The heat treatment operation is believed to result in diffusion of material across the layer boundaries and associated enhancement in adhesion (i.e. diffusion bonding). Interlayer adhesion and maybe intra-layer cohesion may be enhanced by heat treating in the presence of a reducing atmosphere that may help remove weaker oxides from surfaces or even from internal portions of layers.

Abstract translation: 多层微尺度或中尺度结构用粘附层（例如在连续层沉积到先前层上时结合在一起的层）制造，然后进行显着增强层间粘合的热处理操作。 认为热处理操作导致材料在层边界上的扩散，并且附着力增强（即扩散粘合）。 可以通过在有助于从表面甚至从内部部分去除较弱的氧化物的还原气氛的热处理来增强层间粘附和可能的层内内聚力。

公开(公告)号：US20140209473A1

公开(公告)日：2014-07-31

申请号：US14185613

申请日：2014-02-20

Applicant: Microfabrica Inc.

Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Kieun Kim ,  Qui T. Le ,  Gang Zhang ,  Uri Frodis ,  Dale S. McPherson ,  Dennis R. Smalley

IPC: C25D5/02

CPC classification number: C25D5/022 ,  B81C1/00126 ,  B81C2201/0109 ,  B81C2201/019 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  Y10T156/11 ,  Y10T156/19

Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.

Abstract translation: 本发明的一些实施例涉及在电介质或部分电介质基底上建立单层或多层结构的技术。 某些实施方案将种子层材料直接沉积到基底材料上，而其它实施例使用中间粘合层材料。 一些实施例使用不同种子层材料和/或用于牺牲和结构导电建筑材料的粘合层材料。 一些实施例将种子层和/或粘合层材料应用于有选择性的方式，而其它实施例以毯子的方式应用材料。 一些实施例通过平面化操作去除外来沉积物（例如沉积到不想要形成层的一部分的区域），而其他实施例通过蚀刻操作去除外来材料。 其它实施方案涉及使用至少一种导电结构材料，至少一种导电牺牲材料和至少一种电介质材料形成的多层中尺度或微结构结构的电化学制造。 在一些实施方案中，电介质材料是可UV固化的光聚合物。

公开(公告)号：US20140140788A1

公开(公告)日：2014-05-22

申请号：US14054139

申请日：2013-10-15

Applicant: Microfabrica Inc.

Inventor： Uri Frodis, III ,  Adam L. Cohen ,  Christopher R. Folk

IPC: F16B33/02

CPC classification number: F16B33/02

Abstract: Embodiments of the invention provide threaded elements alone, in mating pairs, or in conjunction with other elements. Embodiments of the invention also provide for design and fabrication of such threaded elements without violating minimum feature size design rules or causing other interference issues that may result from the fabrication of such thread elements using a multi-layer multi-material electrochemical fabrication process.

Abstract translation: 本发明的实施例单独提供螺纹元件，配合对中，或与其它元件结合。 本发明的实施例还提供了这种螺纹元件的设计和制造，而不违反最小特征尺寸设计规则或引起使用多层多材料电化学制造工艺制造这种螺纹元件可能导致的其它干扰问题。

公开(公告)号：US20140134453A1

公开(公告)日：2014-05-15

申请号：US14017535

申请日：2013-09-04

Applicant: Microfabrica Inc.

Inventor： Ming Ting Wu ,  Rulon J. Larsen, III ,  Young Kim ,  Kieun Kim ,  Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard ,  Dennis R. Smalley

IPC: B32B15/01

CPC classification number: G01R1/06761 ,  B32B15/01 ,  Y10T428/12486

Abstract: Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that (1) partially coats the surface of the structure, (2) completely coats the surface of the structure, and/or (3) completely coats the surface of structural material of each layer from which the structure is formed including interlayer regions. These embodiments incorporate both the core material and the shell material into the structure as each layer is formed along with a sacrificial material that is removed after formation of all layers of the structure. In some embodiments the core material may be a material that would be removed with sacrificial material if it were accessible by an etchant during removal of the sacrificial material.

Abstract translation: 本发明的一些实施方案涉及用于从核心材料和壳或涂层材料形成结构或器件（例如用于半导体器件的晶片级测试的微探针）的电化学制造方法，（1）部分地涂覆结构的表面 ，（2）完全涂覆结构的表面，和/或（3）完全涂覆包含中间层区域的结构形成的各层结构材料的表面。 这些实施例将芯材料和壳体材料结合到结构中，因为每个层与形成所述结构的所有层之后被去除的牺牲材料一起形成。 在一些实施例中，芯材料可以是如果在去除牺牲材料期间可通过蚀刻剂使用牺牲材料将其去除的材料。

公开(公告)号：US20140008235A1

公开(公告)日：2014-01-09

申请号：US13657375

申请日：2012-10-22

Applicant: Microfabrica Inc.

Inventor： Dennis R. Smalley ,  Adam L. Cohen ,  Ananda H. Kumar ,  Michael S. Lockard

IPC: C25D5/02

CPC classification number: A61N1/00 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  C25D1/20 ,  C25D5/022 ,  G01R1/0483 ,  G01R1/06716 ,  G01R1/07357 ,  G01R31/2886 ,  H05K3/467 ,  H05K3/4682

Abstract: Electrochemical fabrication processes and apparatus for producing multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers including operations for providing coatings of dielectric material that isolate at least portions of a first conductive material from (1) other portions of the first conductive material, (2) a second conductive material, or (3) another dielectric material, and wherein the thickness of the dielectric coatings are thin compared to the thicknesses of the layers used in forming the structures. In some preferred embodiments, portions of each individual layer are encapsulated by dielectric material while in other embodiments only boundaries between distinct regions of materials are isolated from one another by dielectric barriers.

Abstract translation: 用于生产多层结构的电化学制造方法和装置，其中每个层包括至少两种材料的沉积，并且其中形成至少一些层，包括用于提供将第一导电材料的至少一部分与 （1）第一导电材料的其它部分，（2）第二导电材料或（3）另一种电介质材料，并且其中电介质涂层的厚度与用于形成结构的层的厚度相比较薄。 在一些优选实施例中，每个单独层的部分被电介质材料包封，而在其它实施例中，材料的不同区域之间的边界通过电介质屏障彼此隔离。

公开(公告)号：US20140004374A1

公开(公告)日：2014-01-02

申请号：US14017510

申请日：2013-09-04

Applicant: Microfabrica Inc.

Inventor： Adam L. Cohen

IPC: C25D1/00 ,  C25D5/02

CPC classification number: C25D5/10 ,  B33Y10/00 ,  B33Y70/00 ,  B81C1/00126 ,  B81C2201/0181 ,  B81C2201/0197 ,  B81C2201/032 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/12 ,  C25D5/22 ,  C25D17/06 ,  H01L21/2885 ,  H05K3/241 ,  Y10T428/12486 ,  Y10T428/239

Abstract: An electroplating method that includes: a) contacting a first substrate with a first article, which includes a substrate and a conformable mask disposed in a pattern on the substrate; b) electroplating a first metal from a source of metal ions onto the first substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the first substrate, is disclosed. Electroplating articles and electroplating apparatus are also disclosed.

Abstract translation: 一种电镀方法，包括：a）使第一衬底与第一制品接触，所述第一制品包括衬底和以衬底形式设置的贴合掩模; b）以第一图案将来自金属离子源的第一金属电镀到所述第一基板上，所述第一图案对应于所述适形掩模图案的所述补体; 和c）从第一基板上去除第一制品。 还公开了电镀制品和电镀装置。