公开(公告)号：US10242718B2

公开(公告)日：2019-03-26

申请号：US15620490

申请日：2017-06-12

Applicant: Micron Technology, Inc.

Inventor： Joe M. Jeddeloh ,  Brent Keeth

IPC: G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02 ,  G11C11/4063

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

公开(公告)号：US10170389B2

公开(公告)日：2019-01-01

申请号：US14825009

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/10 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L23/36 ,  H01L25/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US20180366443A1

公开(公告)日：2018-12-20

申请号：US15976580

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: H01L25/065

Abstract: Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include a plurality of banks of memory cells. Each region may be associated with a data channel configured to communicate with a host device. In some examples, each channel of the array may include two or more data pins. The ratio of data pins per channel may be two or four in various examples. Other examples may include eight data pins per channel.

公开(公告)号：US20180342294A1

公开(公告)日：2018-11-29

申请号：US16057170

申请日：2018-08-07

Applicant: Micron Technology, Inc.

Inventor： D.V. Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Lei Bi ,  Adam D. Johnson ,  Brent Keeth ,  Alessandro Calderoni ,  Scott E. Sills

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057

Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.

公开(公告)号：US20180158800A1

公开(公告)日：2018-06-07

申请号：US15372246

申请日：2016-12-07

Applicant: Micron Technology, Inc.

Inventor： Adam S. El-Mansouri ,  Fuad Badrieh ,  Brent Keeth

IPC: H01L25/065 ,  G05F1/10

CPC classification number: H01L25/0657 ,  G05F1/10 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.

公开(公告)号：US09934870B2

公开(公告)日：2018-04-03

申请号：US14790485

申请日：2015-07-02

Applicant: Micron Technology, Inc.

Inventor： Joe M. Jeddeloh ,  Brent Keeth

IPC: G06F11/00 ,  G11C29/44 ,  G06F11/20 ,  G06F11/16 ,  G06F11/07 ,  G06F11/10 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/4401 ,  G06F11/073 ,  G06F11/1072 ,  G06F11/1088 ,  G06F11/1666 ,  G06F11/2017 ,  G11C29/702 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/0401 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.

公开(公告)号：US20150380109A1

公开(公告)日：2015-12-31

申请号：US14790485

申请日：2015-07-02

Applicant: Micron Technology, Inc.

Inventor： Joe M. Jeddeloh ,  Brent Keeth

IPC: G11C29/44 ,  G06F11/10 ,  G11C29/00 ,  G06F11/07

CPC classification number: G11C29/4401 ,  G06F11/073 ,  G06F11/1072 ,  G06F11/1088 ,  G06F11/1666 ,  G06F11/2017 ,  G11C29/702 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/0401 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.

Abstract translation: 一些实施例包括具有与处理单元通信的第一接口，与存储器设备通信的第二接口以及耦合到第一和第二接口的模块的设备和方法。 在至少一个实施例中，模块可以被配置为获得存储在存储设备中的信息，并且至少部分地基于该信息来执行对存储器设备的存储器结构的测试和修复中的至少一个。

公开(公告)号：US20150091189A1

公开(公告)日：2015-04-02

申请号：US14563222

申请日：2014-12-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Christopher K. Morzano

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0652 ,  G06F13/385 ,  G11C5/02 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555

Abstract: Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

Abstract translation: 各种实施例包括具有堆叠装置的装置和在接口管芯上形成管芯堆叠的方法。 在一种这样的装置中，骰子堆叠包括至少第一模具和第二模具，以及将第一模具和第二模具耦合到公共控制模具的导电路径。 在一些实施例中，导电路径可以布置成与堆叠的交替管芯上的电路连接。 在其他实施例中，多个骰子堆可以被布置在单个接口管芯上，并且骰子的一些或全部可以具有交错导电路径。

公开(公告)号：US20150029774A1

公开(公告)日：2015-01-29

申请号：US14511794

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/20 ,  G11C2207/2227 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die.

Abstract translation: 一些实施例包括具有布置在堆叠中的骰子的装置和方法。 骰子至少包括第一管芯和第二管芯，以及连接到管芯的连接。 连接可以被配置为在将第一标识分配给第一管芯期间将控制信息传送到第一管芯，并且在将第二标识分配给第二管芯期间将控制信息从第一管芯传送到第二管芯。

公开(公告)号：US20140281199A1

公开(公告)日：2014-09-18

申请号：US14263321

申请日：2014-04-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jacob Baker ,  Brent Keeth

IPC: G11C11/42

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/287 ,  G06F13/4234 ,  G11C11/42 ,  H04B10/802 ,  H04L12/40013 ,  H04Q11/0071 ,  Y02D10/14 ,  Y02D10/151

Abstract: A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.

Abstract translation: 公开了一种用于实现控制器和存储器件之间的电气隔离的光学链路。 光链路增加了电互连的抗噪声能力，并且允许存储器件被放置在距离处理器更远的位置，而不需要耗电的I / O缓冲器。