公开(公告)号：US11074177B2

公开(公告)日：2021-07-27

申请号：US16445738

申请日：2019-06-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

公开(公告)号：US20210181960A1

公开(公告)日：2021-06-17

申请号：US17189502

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He

IPC: G06F3/06 ,  G06F9/4401 ,  G06F11/10 ,  G11C29/52

Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.

公开(公告)号：US20210089444A1

公开(公告)日：2021-03-25

申请号：US17118152

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He ,  David Aaron Palmer

IPC: G06F12/02 ,  G11C11/16 ,  G11C16/10

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a pattern of host accessing the device are discussed. The host access pattern can be represented by how frequent the device is in idle states free of active host access. An exemplary memory device includes a memory controller to track a count of idle periods during a specified time window, and to adjust an amount of memory space to be freed by a GC operation in accordance with the count of idle periods. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the count of idle periods during the specified time window.

公开(公告)号：US20190339891A1

公开(公告)日：2019-11-07

申请号：US16512256

申请日：2019-07-15

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G06F9/4401

Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.

公开(公告)号：US20170242747A1

公开(公告)日：2017-08-24

申请号：US15046666

申请日：2016-02-18

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Sampath K. Ratnam

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/15 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/29 ,  H03M13/2936 ,  H03M13/2966 ,  H03M13/356 ,  H03M13/6356 ,  H04L1/0057 ,  H04L1/0066 ,  H04L1/007 ,  H04L2001/0098

Abstract: The present disclosure includes apparatuses and methods for error rate reduction. One example method comprises adding an amount of error rate reduction (ERR) data to an amount of received user data, and writing the amount of user data along with the amount of ERR data to a memory.

公开(公告)号：US20250117321A1

公开(公告)日：2025-04-10

申请号：US18771713

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Wenjun Wu

IPC: G06F12/02 ,  G06F12/06

Abstract: Methods, systems, and devices for compression-based address mapping management in a memory system are described. A memory system may reduce a quantity of times regions of an address mapping table are transferred between a non-volatile memory and a local memory of the memory system. The memory system may selectively retain regions of the address mapping table in local memory in-between checkpoint procedures. During a checkpoint procedure, the memory system may compress the regions of the address mapping table in the local memory and, if the regions are sufficiently compressible, may keep the regions in the local memory until the next checkpoint procedure.

公开(公告)号：US20250117150A1

公开(公告)日：2025-04-10

申请号：US18776201

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz

IPC: G06F3/06

Abstract: Methods, systems, and devices for data transfer during maintenance operations are described. A memory system utilize an auto-suspend feature to parallelize aspects of maintenance operations. For example, the memory system may suspend a programming operation being performed on a first block of memory cells. The memory system may read data from a second block of memory cells while the programming operation is suspended, and may transfer the data from the second block of memory cells (e.g., to a controller) in parallel with resuming the programming operation on the first block of memory cells. The memory system may transfer the data read from the second block of memory cells to a third block of memory cells in parallel with resuming the programming operation on the first block of memory cells.

公开(公告)号：US12182027B2

公开(公告)日：2024-12-31

申请号：US18095782

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/00 ,  G06F12/0893

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

公开(公告)号：US20240345947A1

公开(公告)日：2024-10-17

申请号：US18037631

申请日：2022-09-01

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

公开(公告)号：US20240319899A1

公开(公告)日：2024-09-26

申请号：US18634584

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Caixia Yang

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0667 ,  G06F3/0673

Abstract: Methods, systems, and devices for assigning blocks of memory systems are described. Some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.