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    THREE DIMENSIONAL MEMORY ARRAYS
    41.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20190067371A1

    公开(公告)日：2019-02-28

    申请号：US15689155

    申请日：2017-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: H01L27/24 ,  H01L45/00 ,  H01L27/115

    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

    THREE DIMENSIONAL MEMORY ARRAY
    42.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：US20180374897A1

    公开(公告)日：2018-12-27

    申请号：US16118632

    申请日：2018-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

    Mixed cross point memory
    43.
    发明授权
    Mixed cross point memory 有权

    公开(公告)号：US10157667B2

    公开(公告)日：2018-12-18

    申请号：US15582321

    申请日：2017-04-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

    IPC: G11C5/06 ,  G11C13/00 ,  G11C11/56

    Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.

    THREE DIMENSIONAL MEMORY ARRAY
    45.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：US20180294312A1

    公开(公告)日：2018-10-11

    申请号：US15482016

    申请日：2017-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

    METHOD, SYSTEM, AND DEVICE FOR L-SHAPED MEMORY COMPONENT
    46.
    发明申请
    METHOD, SYSTEM, AND DEVICE FOR L-SHAPED MEMORY COMPONENT 审中-公开

    公开(公告)号：US20180145250A1

    公开(公告)日：2018-05-24

    申请号：US15858794

    申请日：2017-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/1691

    Abstract: Embodiments disclosed herein may relate to forming reduced size storage components in a cross-point memory array. In an embodiment, a storage cell comprising an L-shaped storage component having an approximately vertical portion extending from a first electrode positioned below the storage material to a second electrode positioned above and/or on the storage component. A storage cell may further comprise a selector material positioned above and/or on the second electrode and a third electrode positioned above and/or on the selector material, wherein the approximately vertical portion of the L-shaped storage component comprises a reduced size storage component in a first dimension.

    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    50.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME 审中-公开

    公开(公告)号：US20170365642A1

    公开(公告)日：2017-12-21

    申请号：US15693102

    申请日：2017-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

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