公开(公告)号：US10964654B2

公开(公告)日：2021-03-30

申请号：US16667360

申请日：2019-10-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

公开(公告)号：US20210057264A1

公开(公告)日：2021-02-25

申请号：US16983559

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/108 ,  H01L23/498 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20200294854A1

公开(公告)日：2020-09-17

申请号：US16826651

申请日：2020-03-23

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L23/48

Abstract: Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.

公开(公告)号：US10529592B2

公开(公告)日：2020-01-07

申请号：US15830839

申请日：2017-12-04

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

公开(公告)号：US20190371755A1

公开(公告)日：2019-12-05

申请号：US16541449

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Kyle K. Kirby ,  Owen R. Fay ,  Sameer S. Vadhavkar

IPC: H01L23/00 ,  H01L23/24 ,  H01L21/56

Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.

公开(公告)号：US10446486B2

公开(公告)日：2019-10-15

申请号：US16007670

申请日：2018-06-13

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially through the first die and a first substantially helical conductor disposed around the first TSV. The second die includes a second TSV coupled to the first TSV and a second substantially helical conductor disposed around the second TSV. The first substantially helical conductor is configured to induce a change in a magnetic field in the first and second TSVs in response to a first changing current in the first substantially helical conductor, and the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.

公开(公告)号：US20190131260A1

公开(公告)日：2019-05-02

申请号：US15797638

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/065

Abstract: A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

公开(公告)号：US20180323369A1

公开(公告)日：2018-11-08

申请号：US15584294

申请日：2017-05-02

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L43/10 ,  H01F27/28 ,  H01L23/535 ,  H01L43/02

CPC classification number: H01L43/10 ,  H01F27/28 ,  H01L23/535 ,  H01L43/02

Abstract: A semiconductor device comprising a substrate is provided. The device further comprises a through-substrate via (TSV) extending into the substrate, and a substantially helical conductor disposed around the TSV. The substantially helical conductor can be configured to generate a magnetic field in the TSV in response to a current passing through the helical conductor. More than one TSV can be included, and/or more than one substantially helical conductor can be provided.

公开(公告)号：US10020287B2

公开(公告)日：2018-07-10

申请号：US14959500

申请日：2015-12-04

Applicant: Micron Technology, Inc.

Inventor： David S. Pratt ,  Kyle K. Kirby ,  Dewali Ray

IPC: H01L25/04 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/043 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/00014

Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.

公开(公告)号：US20170301639A1

公开(公告)日：2017-10-19

申请号：US15583500

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： William M. Hiatt ,  Kyle K. Kirby

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/498

Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.