公开(公告)号：US20220415394A1

公开(公告)日：2022-12-29

申请号：US17898001

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Mingdong Cui ,  Nevil N. Gajera

IPC: G11C13/00

Abstract: A memory device having memory cells, voltage drivers, and a controller configured to determine, based on an attribute of a memory cell, whether to apply a drift cancellation pulse that is in the opposite polarity of a programming pulse configured to place the memory cell in a state to represent a bit of data. If the drift in the state of the memory cell from a previous programming operation to write data into the memory cell is predicted to be insufficient to prevent the selection of the memory cell during the application of the programming pulse, the drift cancellation pulse is skipped. Otherwise, the drift cancellation pulse is applied in the opposite polarity of the programming pulse.

公开(公告)号：US11430518B1

公开(公告)日：2022-08-30

申请号：US17217379

申请日：2021-03-30

Applicant: Micron Technology, Inc.

Inventor： Hongmei Wang ,  Mingdong Cui ,  Nevil N. Gajera

IPC: G11C11/00 ,  G11C13/00

Abstract: A memory device having memory cells, voltage drivers, and a controller configured to determine, based on an attribute of a memory cell, whether to apply a drift cancellation pulse that is in the opposite polarity of a programming pulse configured to place the memory cell in a state to represent a bit of data. If the drift in the state of the memory cell from a previous programming operation to write data into the memory cell is predicted to be insufficient to prevent the selection of the memory cell during the application of the programming pulse, the drift cancellation pulse is skipped. Otherwise, the drift cancellation pulse is applied in the opposite polarity of the programming pulse.

公开(公告)号：US11074970B2

公开(公告)日：2021-07-27

申请号：US16668549

申请日：2019-10-30

Applicant: Micron Technology, Inc.

Inventor： Nathan Joseph Sirocka ,  Mingdong Cui ,  Jeffrey Edward Koelling

IPC: G11C11/00 ,  G11C13/00

Abstract: A decoder in an integrated circuit memory device having: a positive section having a first input line; a negative section having a second input line; and an output line connected from both the positive section and the negative section to a voltage driver connected to a memory cell. The positive section and the negative sections are controlled by a polarity control signal. When the polarity control signal indicates positive polarity, the positive section drives the output line according to signals received in the first input line; and when the polarity control signal indicates negative polarity, the negative section drives the output line according to signals received in the second input line.

公开(公告)号：US20210151103A1

公开(公告)日：2021-05-20

申请号：US17158984

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Michel Ibrahim Ishac

IPC: G11C13/00

Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.

公开(公告)号：US20210118492A1

公开(公告)日：2021-04-22

申请号：US17037497

申请日：2020-09-29

Applicant: Micron Technology, Inc.

Inventor： Nathan Joseph Sirocka ,  Mingdong Cui

IPC: G11C11/413 ,  G11C11/4074 ,  G11C29/50 ,  G11C11/4094 ,  G11C11/408

Abstract: An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.

公开(公告)号：US10930345B1

公开(公告)日：2021-02-23

申请号：US16660590

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Michel Ibrahim Ishac

IPC: G11C11/419 ,  G11C13/00

Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.

公开(公告)号：US10911049B2

公开(公告)日：2021-02-02

申请号：US16517000

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hari Giduturi

IPC: H03K17/10 ,  H03K19/0185 ,  H03K5/003 ,  H03K5/00

Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.

公开(公告)号：US10818345B1

公开(公告)日：2020-10-27

申请号：US16660486

申请日：2019-10-22

Applicant: Micron Technology, Inc.

Inventor： Nathan Joseph Sirocka ,  Mingdong Cui

IPC: G11C11/41 ,  G11C11/413 ,  G11C11/4074 ,  G11C29/50 ,  G11C11/408 ,  G11C11/4094 ,  G11C5/14

Abstract: An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.

公开(公告)号：US09870820B2

公开(公告)日：2018-01-16

申请号：US15470492

申请日：2017-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/50004 ,  G11C2013/009 ,  G11C2029/5004 ,  G11C2213/72 ,  G11C2213/76

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US09245597B2

公开(公告)日：2016-01-26

申请号：US14287946

申请日：2014-05-27

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Mingdong Cui

IPC: G11C5/14 ,  G11C7/06 ,  G11C7/14 ,  G11C13/00 ,  G05F3/16 ,  G11C8/08

CPC classification number: G11C13/004 ,  G05F1/461 ,  G05F3/16 ,  G11C5/147 ,  G11C7/062 ,  G11C7/14 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0038 ,  G11C2013/0054

Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.

Abstract translation: 所描述的示例包括用于向感测电路提供参考电压的感测电路和参考电压发生器。 感测电路可以感测可以是PCM存储器单元的存储器单元的状态。 感测电路可以包括共源共栅晶体管。 参考电压发生器的示例可以包括耦合到多个组参考电压发生器的全局参考电压发生器，其可以减小电压发生器路由的输出电阻。