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公开(公告)号：US09396063B2
公开(公告)日：2016-07-19
申请号：US14276002
申请日：2014-05-13
Applicant: Macronix International Co., Ltd.
Inventor： Ren-Shuo Liu , Meng-Yen Chuang , Chia-Lin Yang , Cheng-Hsuan Li , Kin-Chu Ho , Hsiang-Pang Li
CPC classification number: G06F11/1048 , G06F11/1016
Abstract: An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.
Abstract translation: 提供了一种存储装置的操作方法。 操作方法包括以下步骤。 首先，从第一存储单元的目标地址读取第一数据。 然后，辅助单元检查目标地址是否对应于存储在第二存储单元中的第二数据。 如果目标地址对应于第二数据，则辅助单元根据第二数据更新第一数据以产生更新的数据。 接下来，纠错码（ECC）对更新后的数据进行解码处理，生成译码后的数据。
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公开(公告)号：US20150178010A1
公开(公告)日：2015-06-25
申请号：US14523006
申请日：2014-10-24
Applicant: Macronix International Co., Ltd.
Inventor： Ping-Chun Chang , Yuan-Hao Chang , Hung-Sheng Chang , Tei-Wei Kuo , Hsiang-Pang Li
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/064 , G06F3/0644 , G06F3/0679 , G06F12/023 , G06F12/0238 , G06F12/0292 , G06F2212/1024 , G06F2212/202 , G06F2212/214 , G06F2212/7201
Abstract: A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications. The plurality of physical memory segments is allocated to corresponding logical addresses based on the plurality of classifications, and on usage statistics of the physical memory segments. A data structure is maintained recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments. The plurality of classifications includes a first classification and a second classification having different usage statistic requirements than the first classification. Logical addresses having the second classification can be redirected to physical segments allocated to logical addresses having the first classification, and the data structure can be updated to record redirected logical addresses. A free command can release a physical memory segment allocated for main memory use.
Abstract translation: 提供了一种用于管理包括多个物理存储器段的存储器件的方法。 逻辑存储器空间根据使用规范被分类为多个分类。 基于多个分类，以及物理存储器段的使用统计，将多个物理存储器段分配给相应的逻辑地址。 数据结构保持在逻辑存储器空间中的逻辑地址和物理存储器段的物理地址之间进行记录转换。 多个分类包括与第一分类不同的使用统计要求的第一分类和第二分类。 具有第二分类的逻辑地址可以被重定向到分配给具有第一分类的逻辑地址的物理段，并且可以更新数据结构以记录重定向的逻辑地址。 免费命令可以释放分配给主内存使用的物理内存段。
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公开(公告)号：US20140307505A1
公开(公告)日：2014-10-16
申请号：US14060296
申请日：2013-10-22
Applicant: Macronix International Co., Ltd
Inventor： Yu-Ming Chang , Yung-Chun Li , Hsing-Chen Lu , Hsiang-Pang Li , Cheng-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G11C16/34
CPC classification number: G06F12/0246 , G06F2212/7205 , G11C16/0483 , G11C16/16 , G11C16/3427
Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.
Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。
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公开(公告)号：US20140189276A1
公开(公告)日：2014-07-03
申请号：US13939948
申请日：2013-07-11
Applicant: Macronix International Co., Ltd.
Inventor： Hung-Sheng Chang , Cheng-Yuan Wang , Hsiang-Pang Li , Yuan-Hao Chang , Pi-Cheng Hsiu , Tei-Wei Kuo
IPC: G06F12/02
CPC classification number: G06F12/0238 , G06F12/0246 , G06F12/109 , G06F2212/1032 , G06F2212/7204 , G06F2212/7211
Abstract: A method is provided for managing a file system including data objects. The data objects, indirect pointers and source pointers are stored in containers that have addresses and include addressable units of a memory. The objects are mapped to addresses for corresponding containers. The indirect pointer in a particular container points to the address of a container in which the corresponding object is stored. The source pointer in the particular container points to the address of the container to which the object in the particular container is mapped. An object in a first container is moved to a second container. The source pointer in the first container is used to find a third container to which the object is mapped. The indirect pointer in the third container is updated to point to the second container. The source pointer in the second container is updated to point to the third container.
Abstract translation: 提供了一种用于管理包括数据对象的文件系统的方法。 数据对象，间接指针和源指针存储在具有地址并包含存储器可寻址单元的容器中。 对象映射到相应容器的地址。 特定容器中的间接指针指向存储相应对象的容器的地址。 特定容器中的源指针指向特定容器中的对象映射到的容器的地址。 将第一容器中的物体移动到第二容器。 第一个容器中的源指针用于查找对象映射到的第三个容器。 第三个容器中的间接指针被更新为指向第二个容器。 第二个容器中的源指针被更新为指向第三个容器。
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公开(公告)号：US11526328B2
公开(公告)日：2022-12-13
申请号：US16781868
申请日：2020-02-04
Applicant: MACRONIX International Co., Ltd.
Inventor： Hung-Sheng Chang , Han-Wen Hu , Hsiang-Pang Li , Tzu-Hsien Yang , I-Ching Tseng , Hsiang-Yun Cheng , Chia-Lin Yang
Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.
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Patent Agency Ranking
46.发明授权公开(公告)号：US11194515B2
公开(公告)日：2021-12-07
申请号：US16571249
申请日：2019-09-16
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ping-Hsien Lin , Wei-Chen Wang , Hsiang-Pang Li , Shu-Hsien Liao , Che-Wei Tsao , Yuan-Hao Chang , Tei-Wei Kuo
Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.
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公开(公告)号：US20210240443A1
公开(公告)日：2021-08-05
申请号：US16781868
申请日：2020-02-04
Applicant: MACRONIX International Co., Ltd.
Inventor： Hung-Sheng Chang , Han-Wen Hu , Hsiang-Pang Li , Tzu-Hsien Yang , I-Ching Tseng , Hsiang-Yun Cheng , Chia-Lin Yang
Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.
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48.发明授权公开(公告)号：US11050440B2
公开(公告)日：2021-06-29
申请号：US16658191
申请日：2019-10-21
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chih-Huai Shih , Yu-Ming Huang , Hsiang-Pang Li , Hsi-Chia Chang
Abstract: An encoding method includes: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.
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公开(公告)号：US20180166148A1
公开(公告)日：2018-06-14
申请号：US15614654
申请日：2017-06-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Huang , Hsiang-Pang Li , Kun-Cheng Hsu , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G11C29/44 , G06F11/27 , G11C8/14 , G11C29/10 , G11C2029/1202
Abstract: A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a code word through a polar code transformation. Select a boundary bit-channel among the bit-channels according to a first ranking list for the bit-channels. Identify a target memory cell among the memory cells according to the boundary bit-channel and a generator matrix of the polar code transformation. Decrease a raw bit error rate of the target memory cell.
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公开(公告)号：US09760488B2
公开(公告)日：2017-09-12
申请号：US14825204
申请日：2015-08-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hung-Sheng Chang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G06F12/08 , G06F12/0815 , G06F12/0811 , G06F12/1009
CPC classification number: G06F12/0815 , G06F12/0811 , G06F12/0893 , G06F12/1009 , G06F12/1027 , G06F2212/1021 , G06F2212/283 , G06F2212/608
Abstract: A cache system is provided. The cache system includes a first cache and a second cache. The first cache is configured for storing a first status of a plurality of data. The second cache is configured for storing a table. The table includes the plurality of data arranged from a highest level to a lowest level. The cache system is configured to update the first status of the plurality of data in the first cache. The cache system is further configured to update the table in the second cache according to the first status of the plurality of data.
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