公开(公告)号：USRE37308E1

公开(公告)日：2001-08-07

申请号：US08376300

申请日：1995-01-23

申请人： Paolo G. Cappelletti ,  Giuseppe Corda ,  Carlo Riva

发明人： Paolo G. Cappelletti ,  Giuseppe Corda ,  Carlo Riva

IPC分类号： H01L29788

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n+ diffusion which is closed and isolated from those of the other cells of the same memory.

摘要翻译： 电池由选择晶体管，检测晶体管和隧道冷凝器形成。 检测晶体管具有形成有n +扩散的其自己的控制栅极，其与相同存储器的其它单元的封闭隔离。

公开(公告)号：US6004847A

公开(公告)日：1999-12-21

申请号：US667097

申请日：1996-06-20

申请人： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

发明人： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.

摘要翻译： 一种用于形成集成电路的工艺包括至少一个非易失性存储单元阵列，其具有至少包含下介电材料层和上氧化硅层的中间介电层。 该集成电路包括至少一个晶体管，同时形成在基体周边的区域中，并且具有第一厚度的栅极电介质。 在形成具有栅极氧化物层和多晶硅层的浮置栅极和形成下部电介质材料层之后，该工艺包括从基体的周边区域去除所述层; 所述上氧化硅层沉积在所述存储单元上，并在所述外围晶体管的区域中的衬底上; 以及至少在周边晶体管的区域中形成第一氧化硅层。 第二晶体管类型可以在连续的步骤中形成具有比所述第一厚度更薄的第二厚度的栅极电介质。

公开(公告)号：US5977591A

公开(公告)日：1999-11-02

申请号：US824888

申请日：1997-03-18

申请人： Lorenzo Fratin ,  Carlo Riva

发明人： Lorenzo Fratin ,  Carlo Riva

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/4983 ,  H01L21/28105 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7836

摘要： A MOS transistor capable of withstanding relatively high voltages is of a type integrated on a region included in a substrate of semiconductor material, having conductivity of a first type and comprising a channel region intermediate between a first active region of source and a second active region of drain. Both these source and drain regions have conductivity of a second type and extend from a first surface of the substrate. The transistor also has a gate which includes at least a first polysilicon layer overlying the first surface of at least the channel region, to which it is coupled capacitively through a gate oxide layer. According to the invention, the first polysilicon layer includes a mid-portion which only overlies the channel region and has a first total conductivity of the first type, and a peripheral portion with a second total conductivity differentiated from the first total conductivity. The peripheral portion partly overlies the source and drain active regions toward the channel region.

摘要翻译： 能够承受相对高电压的MOS晶体管是集成在包括在半导体材料的衬底中的区域上的类型，其具有第一类型的导电性并且包括在源的第一有源区和第二有源区之间的沟道区 排水。 这些源极和漏极区都具有第二类型的导电性并且从衬底的第一表面延伸。 晶体管还具有栅极，该栅极至少包括覆盖至少沟道区的第一表面的第一多晶硅层，其通过栅极氧化物层电容耦合到该栅极氧化物层。 根据本发明，第一多晶硅层包括仅覆盖沟道区并具有第一类型的第一总电导率的中间部分，以及与第一总电导率不同的具有第二总电导率的外围部分。 外围部分部分地覆盖源极和漏极有源区域朝向沟道区域。

公开(公告)号：US5936298A

公开(公告)日：1999-08-10

申请号：US761185

申请日：1996-12-06

申请人： Piero Capocelli ,  Raffaele Zambrano ,  Federico Pio ,  Carlo Riva

发明人： Piero Capocelli ,  Raffaele Zambrano ,  Federico Pio ,  Carlo Riva

IPC分类号： H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L29/00

CPC分类号： H01F41/046 ,  H01F17/0033 ,  H01L23/5227 ,  H01F2017/0086 ,  H01L2924/0002

摘要： Inductive structures make highly efficient use of the magnetic flux generd, and are consistent with integrated circuit manufacturing techniques. The structures include electrically conductive layers and interconnecting conductor filled vias to define a helical winding surrounding a closed magnetic core. The magnetic core may also be formed by semiconductor manufacturing techinuqes. A method of making the structures on a semiconductor substrate concurrently with the formation of the integrated circuit itself is also disclosed.

摘要翻译： 感应结构高效地利用所产生的磁通量，并与集成电路制造技术保持一致。 这些结构包括导电层和互连导体填充的通孔，以限定围绕封闭磁芯的螺旋绕组。 磁芯也可以由半导体制造技术形成。 还公开了与形成集成电路本身同时在半导体衬底上制造结构的方法。

公开(公告)号：US5936276A

公开(公告)日：1999-08-10

申请号：US883405

申请日：1997-06-26

申请人： Alfonso Maurelli ,  Carlo Riva

发明人： Alfonso Maurelli ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/72

CPC分类号： H01L29/66825 ,  H01L29/7885

摘要： A flash EEPROM memory cell comprises source and drain regions defining a channel region therebetween, a floating gate and a control gate. The source and drain regions are first and second doped semiconductor regions of a first conductivity type formed in a first active area region of a semiconductor material layer of a second conductivity type; the control gate comprises a third doped semiconductor region of the first conductivity type formed in a second active area region of the semiconductor material layer; and the floating gate comprises a polysilicon strip insulatively disposed over the channel region and insulatively extending over the third doped semiconductor region.

摘要翻译： 闪存EEPROM存储单元包括限定其间的沟道区的源区和漏区，浮置栅和控制栅。 源区和漏区是形成在第二导电类型的半导体材料层的第一有源区中的第一和第二掺杂半导体区， 控制栅极包括形成在半导体材料层的第二有源区域中的第一导电类型的第三掺杂半导体区域; 并且浮置栅极包括绝缘地设置在沟道区域上并在第三掺杂半导体区域上绝缘地延伸的多晶硅条。

公开(公告)号：US5915185A

公开(公告)日：1999-06-22

申请号：US062859

申请日：1998-04-20

申请人： Lorenzo Fratin ,  Carlo Riva

发明人： Lorenzo Fratin ,  Carlo Riva

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/4238 ,  H01L21/26586 ,  H01L21/28123 ,  H01L29/0847

摘要： The method includes the following steps: delimiting active areas on a substrate, forming gate electrodes insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation to a reference line on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length, the widths of the gate electrode strips are determined at the design stage in relation to the orientation of the strips to the reference line and on the orientation of the directions of the implant beams.

摘要翻译： 该方法包括以下步骤：限定衬底上的有源区域，在有源区上形成与衬底绝缘的栅电极，并且用衬底的前表面进行多个注入步骤，以形成源区和漏区， 使用栅电极作为掩模。 注入束的方向由与前表面的倾斜角和通过前表面上的参考线的取向限定。 为了避免执行大量的植入步骤而没有前后通道的均匀和恒定的长度，栅极电极条的宽度在设计阶段相对于条与基准线的取向和植入物方向的取向相关来确定 梁。

公开(公告)号：US5792670A

公开(公告)日：1998-08-11

申请号：US475671

申请日：1995-06-06

申请人： Federico Pio ,  Carlo Riva

发明人： Federico Pio ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A method for programming a two-level polysilicon EEPROM memory cell, which cell is implemented in MOS technology on a semiconductor substrate and comprises a floating gate transistor and a further control gate overlying the floating gate with a dielectric layer therebetween, provides for the application of a negative voltage to the control gate during the cell write phase. This enables the voltages being applied across the thin tunnel oxide layer to be distributed so as to reduce the maximum amount of energy of the "holes" and improve the oxide reliability. In addition, by controlling the rise speed of the impulse to the drain region during the write phase, and of the impulse to the control gate during the erase phase, the maximum current flowing through the tunnel oxide can be set and the electric field being applied to the tunnel oxide kept constant, thereby the device life span can be extended.

摘要翻译： 一种用于编程两电平多晶硅EEPROM存储单元的方法，该单元在半导体衬底上的MOS技术中实现，并且包括浮置栅晶体管和覆盖浮置栅极的其它控制栅极，其间具有介电层， 在单元写入阶段期间向控制栅极施加负电压。 这使得施加在薄隧道氧化物层上的电压被分布，以便减少“孔”的最大能量并提高氧化物的可靠性。 此外，通过在写入阶段期间控制到漏极区域的脉冲的上升速度以及在擦除阶段期间对控制栅极的脉冲的上升速度，可以设定流过隧道氧化物的最大电流并施加电场 隧道氧化物保持恒定，从而可延长设备使用寿命。

公开(公告)号：US5527728A

公开(公告)日：1996-06-18

申请号：US329309

申请日：1994-10-26

申请人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

发明人： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7883 ,  H01L27/115 ,  Y10S438/911 ,  Y10S438/981

摘要： A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

摘要翻译： 一种用于在电可擦除和可编程只读存储器单元中形成薄氧化物部分的方法，包括使用增强的氧化效应和重掺杂的横向扩散，以获得其尺寸小于光刻方法的分辨率的隧道部分 用过的。

公开(公告)号：US4956569A

公开(公告)日：1990-09-11

申请号：US373203

申请日：1989-06-30

申请人： Marco Olivo ,  Luigi Pascucci ,  Carlo Riva ,  Paolo Rosini ,  Corrado Villa

发明人： Marco Olivo ,  Luigi Pascucci ,  Carlo Riva ,  Paolo Rosini ,  Corrado Villa

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K3/356 ,  H03K3/3565 ,  H03K19/003

CPC分类号： H03K19/00315 ,  H03K3/356104 ,  H03K3/3565

摘要： A CMOS logic circuit for converting a low voltage logic signal with a range O-VCC into a high voltage logic signal with a range O-VPP, which may be entirely made with enhancement-type transistors, comprises an additional p-channel, decoupling transistor functionally connected in series with the p-channel transistor of the CMOS circuit which is connected to the high voltage node VPP and the additional decoupling transistor is driven by a bias voltage tied to the VPP voltage and lower than the latter by a certain preset value. The so-called gated breakdown of p-channel transistors is effectively prevented and furthermore these circuits, destined to operate under a high supply voltage, may be fabricated through a normal CMOS fabrication process not requiring particular fabrication techniques for the p-channel transistors subject to gated breakdown conditions or the formation of depletion-type transistors and without the use of special circuits which require oscillator generated driving signals.

公开(公告)号：US4823316A

公开(公告)日：1989-04-18

申请号：US119498

申请日：1987-11-12

申请人： Carlo Riva

发明人： Carlo Riva

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00 ,  G11C11/40

CPC分类号： H01L29/7883

摘要： The memory cell comprises a selection transistor, pickup transistor and a tunnel condenser formed using a single layer of polysilicon. The tunnel condenser is formed on an active area distinct and separate from that of the pickup transistor.

摘要翻译： 存储单元包括选择晶体管，拾取晶体管和使用单层多晶硅形成的隧道电容器。 隧道冷凝器形成在与拾取晶体管不同且分离的有源区域上。