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162 条记录 (耗时 0.031 秒)

    Rotational fill techniques for injection molding of solder
    44.
    发明授权
    Rotational fill techniques for injection molding of solder 失效
    用于注射成型焊料的旋转填充技术

    公开(公告)号：US07416104B2

    公开(公告)日：2008-08-26

    申请号：US11409232

    申请日：2006-04-21

    申请人： Steven A. Cordes ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

    发明人： Steven A. Cordes ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

    IPC分类号： B23K31/02

    CPC分类号： B23K3/0638 ,  B23K35/02 ,  B23K2101/40 ,  H01L2224/11

    摘要： A system and method for injection molding conductive bonding material into a plurality of cavities in a non-rectangular mold is disclosed. The method comprises aligning a fill head with a non-rectangular mold. The non-rectangular mold includes a plurality of cavities. The fill head is placed in substantial contact with the non-rectangular mold. Rotational motion is provided to at least one of the non-rectangular mold and the fill head while the fill head is in substantial contact with the non-rectangular mold. Conductive bonding material is forced out of the fill head toward the non-rectangular mold. The conductive bonding material is provided into at least one cavity of the plurality of cavities contemporaneous with the at least one cavity being in proximity to the fill head.

    摘要翻译： 公开了一种用于将导电接合材料注射成非矩形模具中的多个空腔的系统和方法。 该方法包括将填充头与非矩形模具对准。 非矩形模具包括多个空腔。 填充头被放置成与非矩形模具基本接触。 旋转运动提供给非矩形模具和填充头中的至少一个，同时填充头基本上与非矩形模具接触。 将导电接合材料从填充头推向非矩形模具。 导电接合材料被提供到与填充头附近的至少一个空腔同时的多个空腔的至少一个空腔中。

    CHIP SYSTEM ARCHITECTURE FOR PERFORMANCE ENHANCEMENT, POWER REDUCTION AND COST REDUCTION
    48.
    发明申请
    CHIP SYSTEM ARCHITECTURE FOR PERFORMANCE ENHANCEMENT, POWER REDUCTION AND COST REDUCTION 有权
    用于性能提升，降低功耗和降低成本的芯片系统架构

    公开(公告)号：US20070290315A1

    公开(公告)日：2007-12-20

    申请号：US11538567

    申请日：2006-10-04

    申请人： Philip G. Emma ,  John U. Knickerbocker ,  Cirag S. Patel

    发明人： Philip G. Emma ,  John U. Knickerbocker ,  Cirag S. Patel

    IPC分类号： H01L23/02

    CPC分类号： H01L25/0657 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A computer chip is structured to have at least one single-layered chip, at least one multi-layered chip stack, and a carrier package characterized by electrical interconnections of less than 100 microns diameter, wherein the single-layered chip and the multi-layered chip stack are each electrically coupled to the electrical interconnections of the carrier package, and the single-layered chip is communicatively coupled to the multi-layered chip stack through the carrier package so that an electrical signal propagates over a given distance between the single-layered chip and the multi-layered chip stack at substantially a speed of propagation for a single layer chip over the given distance. The single-layered chip can be a processor having multi-cores and the multi-layered chip stack can be a memory cache stack. Interconnect vias, having a density at least as great as 2500 interconnects/cm2 electrically couple the single-layered chip and the multi-layered chip stack to the carrier package.

    摘要翻译： 计算机芯片被构造成具有至少一个单层芯片，至少一个多层芯片堆叠和以小于100微米直径的电互连为特征的载体封装，其中单层芯片和多层芯片 芯片堆叠都电耦合到载体封装的电互连，并且单层芯片通过载体封装通信地耦合到多层芯片堆叠，使得电信号在单层之间传递给定距离 芯片和多层芯片堆栈，在给定距离内的单层芯片基本上是传播速度。 单层芯片可以是具有多核的处理器，并且多层芯片堆栈可以是存储器高速缓存堆栈。 具有至少高达2500个互连/ cm 2的密度的互连通孔将单层芯片和多层芯片堆叠电耦合到载体封装。

    Optical land grid array interposer
    50.
    发明授权
    Optical land grid array interposer 失效

    公开(公告)号：US06819813B2

    公开(公告)日：2004-11-16

    申请号：US10242152

    申请日：2002-09-11

    申请人： Stephen R. Howland ,  John U. Knickerbocker ,  Steven P. Ostrander ,  Martin L. Schmatz

    发明人： Stephen R. Howland ,  John U. Knickerbocker ,  Steven P. Ostrander ,  Martin L. Schmatz

    IPC分类号： G02B612

    CPC分类号： G02B6/43 ,  G02B6/12002 ,  G02B6/4204

    摘要： An apparatus for integrating optical devices between a module and a circuit board comprising a carrier having optical waveguides, a module having optical ports on a surface of the module, the surface of the module connected to the carrier such that the optical waveguides are in communication with the optical ports; and a circuit board having optical ports on a surface of the circuit board, the surface of the circuit board connected to the carrier such that the optical waveguides are in communication with the optical ports. The apparatus may also integrate electrical ports on the surface of the module, the surface of the circuit board, and electrical connections on the carrier. The apparatus may also integrate circuit chips having optical ports for communication with the optical waveguides.