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    Method and equipment for manufacturing semiconductor device
    41.
    发明授权
    Method and equipment for manufacturing semiconductor device 失效
    制造半导体器件的方法和设备

    公开(公告)号：US06207591B1

    公开(公告)日：2001-03-27

    申请号：US09190444

    申请日：1998-11-13

    申请人： Nobutoshi Aoki ,  Ichiro Mizushima

    发明人： Nobutoshi Aoki ,  Ichiro Mizushima

    IPC分类号： H01L2126

    CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/28167 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/67115 ,  H01L21/823857

    摘要： A silicon wafer is heated from an initial pre-heating temperature (T0) up to a first annealing temperature (T1) by a rapid heating up step using an IR lamp. A first annealing is executed at the first annealing temperature (T1). Successively, while the silicon wafer is maintained at a second annealing temperature (T2) lower than the first annealing temperature (T1), a second annealing step is executed by a resistive heating furnace. A thermal oxidation can be executed as the second annealing step. To do so, an equipment for manufacturing a semiconductor device in the present invention is provided with: a heating device having an IR lamp and a resistive heater; an annealing tube having on a surface thereof a plurality of concave portions in such a way that each bottom approaches a central line; a resistive heater wrapped around this annealing tube; and an IR lamp movably inserted into and pulled out from the concave portion from the external. A IR lamp moving unit for moving the IR lamp is connected to the IR lamp. A wafer loader for mounting a plurality of wafers can be carried into and from the annealing tube. The first annealing step using the IR lamp at the rapid heating rate and successively the second annealing step using the resistive heater are performed on the plurality of wafers without performing a cooling step down to the room temperature. Accordingly, it is possible to effectively recover the damage induced by ion implantation and the like and also possible to suppress the enhanced diffusion of impurity resulting from the,damage to thereby improve the controllability of impurity distribution profile.

    摘要翻译： 通过使用IR灯的快速升温步骤将硅晶片从初始预热温度（T0）加热到第一退火温度（T1）。 在第一退火温度（T1）下执行第一退火。 接下来，当硅晶片保持在低于第一退火温度（T1）的第二退火温度（T2）时，通过电阻加热炉执行第二退火步骤。 作为第二退火工序，可以进行热氧化。 为此，本发明的半导体装置的制造装置具备：具有IR灯和电阻加热器的加热装置; 退火管在其表面上具有多个凹部，使得每个底部接近中心线; 围绕该退火管缠绕的电阻加热器; 以及从外部可移动地插入并从凹部中拉出的IR灯。 用于移动IR灯的IR灯移动单元连接到IR灯。 用于安装多个晶片的晶片加载器可以被携带到退火管中和从退火管中。 在多个晶片上执行以快速加热速率使用IR灯的第一退火步骤以及使用电阻加热器的第二退火步骤，而不进行至室温的冷却步骤。 因此，可以有效地回收由离子注入等引起的损伤，并且还可以抑制由于损伤引起的杂质的增强扩散，从而提高杂质分布特性的可控性。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    42.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20120146128A1

    公开(公告)日：2012-06-14

    申请号：US13364588

    申请日：2012-02-02

    申请人： Takashi Izumida ,  Nobutoshi Aoki

    发明人： Takashi Izumida ,  Nobutoshi Aoki

    IPC分类号： H01L27/088

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11578 ,  H01L27/11582

    摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

    摘要翻译： 在设置有沿方向排列的存储单元晶体管和选择晶体管以选择存储单元晶体管的非易失性半导体存储器件中，电荷陷阱型的每个存储单元晶体管至少由第一绝缘层和第一栅极 电极，并且选择晶体管至少由第二绝缘层和第二栅电极组成。 第一栅电极设置有形成在第一绝缘层上的第一宽度的第一硅化物层。 第二栅电极设置有形成在第二绝缘层上的杂质掺杂硅层，以及形成在杂质掺杂硅层上的第二宽度的第二硅化物层。 第二硅化物具有与第一硅化物相同的组成。 第二宽度大于第一宽度。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    43.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120003801A1

    公开(公告)日：2012-01-05

    申请号：US13224449

    申请日：2011-09-02

    申请人： Takashi Izumida ,  Nobutoshi Aoki

    发明人： Takashi Izumida ,  Nobutoshi Aoki

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7851 ,  H01L29/1054 ,  H01L29/66795

    摘要： A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.

    摘要翻译： 半导体器件具有半导体衬底，形成在半导体衬底上的具有长边方向和短边方向的半导体鳍片，并且具有包含杂质的含碳硅膜和形成在其上的硅膜 含碳硅膜，形成为在短边方向上面对半导体翅片的两侧面的栅电极，分别形成在长边方向两侧的半导体翅片中的源区和漏区 半导体鳍片的方向以夹着栅极电极;以及元件隔离绝缘膜，其形成在半导体鳍片的侧表面上以及栅电极和半导体衬底之间。

    NONVOLATILE SEMICONDUCTOR MEMORY
    44.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY 有权
    非易失性半导体存储器

    公开(公告)号：US20110303958A1

    公开(公告)日：2011-12-15

    申请号：US13156702

    申请日：2011-06-09

    申请人： Kouji MATSUO ,  Toshiyuki Enda ,  Nobutoshi Aoki ,  Toshihiko Iinuma

    发明人： Kouji MATSUO ,  Toshiyuki Enda ,  Nobutoshi Aoki ,  Toshihiko Iinuma

    IPC分类号： H01L29/792 ,  H03K19/08 ,  H01L21/336

    CPC分类号： H01L29/7926 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/24

    摘要： According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.

    摘要翻译： 根据一个实施例，非易失性半导体存储器包括以阵列形式提供的控制栅极，通过第一半导体层的控制栅极，第一半导体层和控制栅极之间的数据记录层，两个第一导电型扩散层 在第一半导体层的第一方向上结束，在第一半导体层的第二方向上的两端处的两个第二导电型扩散层，在第一半导体层上沿第一方向延伸的选择栅极线， 选择栅极线上的第二个方向。 选择栅极线用作连接在控制栅极和沿第一方向布置的字线之间的选择晶体管共享的选择栅极。 每条字线通常连接到沿第二方向布置的控制门。

    SEMICONDUCTOR DEVICE HAVING TRI-GATE STRUCTURE AND MANUFACTURING METHOD THEREOF
    46.
    发明申请
    SEMICONDUCTOR DEVICE HAVING TRI-GATE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    具有三门结构的半导体器件及其制造方法

    公开(公告)号：US20090289293A1

    公开(公告)日：2009-11-26

    申请号：US12470030

    申请日：2009-05-21

    申请人： Takashi IZUMIDA ,  Takahisa Kanemura ,  Nobutoshi Aoki

    发明人： Takashi IZUMIDA ,  Takahisa Kanemura ,  Nobutoshi Aoki

    IPC分类号： H01L29/788 ,  H01L21/28

    CPC分类号： H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.

    摘要翻译： 本发明实施例的半导体器件包括为存储单元提供的存储单元和选择栅极晶体管。 选择栅极晶体管的栅电极具有三栅结构，其中形成在选择栅极晶体管的沟道上方的栅极绝缘膜的上表面被设定为高于栅极绝缘膜的元件隔离区的上表面的一部分 选择栅极晶体管。