公开(公告)号：US08450156B2

公开(公告)日：2013-05-28

申请号：US13481969

申请日：2012-05-29

申请人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

发明人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

IPC分类号： H01L21/332

CPC分类号： H01L29/78624 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.

摘要翻译： 在晶闸管的制造方法中，在基板上或上方形成有第一和第二连接区域， 第一连接区域掺杂有第一导电类型的掺杂剂原子，并且第二连接区域掺杂有第二导电类型的掺杂剂原子; 第一和第二体区域形成在连接区域之间，其中第一体区形成在第一连接区域和第二体区域之间，第二体区域形成在第一体区域和第二连接区域之间; 所述第一体区掺杂有所述第二导电类型的掺杂剂原子，并且所述第二体区掺杂有所述第一导电类型的掺杂剂原子，其中所述掺杂剂原子在每种情况下使用Vt注入方法引入相应的体区; 在身体区域上或上方形成栅极区域。

公开(公告)号：US20120252172A1

公开(公告)日：2012-10-04

申请号：US13481969

申请日：2012-05-29

申请人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

发明人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

IPC分类号： H01L21/332

CPC分类号： H01L29/78624 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.

摘要翻译： 在晶闸管的制造方法中，在基板上或上方形成有第一和第二连接区域， 第一连接区域掺杂有第一导电类型的掺杂剂原子，并且第二连接区域掺杂有第二导电类型的掺杂剂原子; 第一和第二体区域形成在连接区域之间，其中第一体区形成在第一连接区域和第二体区域之间，第二体区域形成在第一体区域和第二连接区域之间; 所述第一体区掺杂有所述第二导电类型的掺杂剂原子，并且所述第二体区掺杂有所述第一导电类型的掺杂剂原子，其中所述掺杂剂原子在每种情况下都使用Vt注入法引入所述体区; 在身体区域上或上方形成栅极区域。

公开(公告)号：US08236624B2

公开(公告)日：2012-08-07

申请号：US12620930

申请日：2009-11-18

申请人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

发明人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

IPC分类号： H01L21/332

CPC分类号： H01L29/78624 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

摘要翻译： 在电子部件的制造方法中，在基板上或上方形成第一掺杂连接区域和第二掺杂连接区域， 在所述第一掺杂连接区域和所述第二掺杂连接区域之间形成体区; 在身体区域上或上方形成彼此分离的至少两个栅极区域; 通过引入掺杂剂原子来掺杂体区的至少一个部分区域，其中通过形成在至少两个分开的栅极区域之间的至少一个中间区域将掺杂剂原子引入到体区的至少一个部分区域中 。

公开(公告)号：US07838939B2

公开(公告)日：2010-11-23

申请号：US11750660

申请日：2007-05-18

申请人： Christian Russ ,  Harald Gossner ,  Michael Fulde

发明人： Christian Russ ,  Harald Gossner ,  Michael Fulde

IPC分类号： H01L23/62

CPC分类号： H01L29/7391 ,  H01L27/0255 ,  H01L27/0814 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/868

摘要： According to one embodiment of the present invention, an ESD protection element for use in an electrical circuit is provided, including a plurality of diodes which are connected in series with one another and which are formed in a contiguous active area, wherein the ESD protection element has a fin structure.

摘要翻译： 根据本发明的一个实施例，提供了一种用于电路中的ESD保护元件，包括彼此串联连接并形成在连续有源区中的多个二极管，其中ESD保护元件 有鳍结构。

公开(公告)号：US20100117116A1

公开(公告)日：2010-05-13

申请号：US12690778

申请日：2010-01-20

申请人： Ulrich Glaser ,  Harald Gossner ,  Kai Esmark

发明人： Ulrich Glaser ,  Harald Gossner ,  Kai Esmark

IPC分类号： H01L29/87

CPC分类号： H01L29/7436 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0814 ,  H01L27/0817 ,  H01L29/87 ,  H01L2924/0002 ,  Y10S438/919 ,  Y10S438/922 ,  Y10S438/923 ,  H01L2924/00

摘要： An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having improved electrical properties, in particular with regard to the use as an ESD protection element.

公开(公告)号：US20090283810A1

公开(公告)日：2009-11-19

申请号：US12511845

申请日：2009-07-29

申请人： Kai Esmark ,  Harald Gossner ,  Christian Russ ,  Jens Schneider

发明人： Kai Esmark ,  Harald Gossner ,  Christian Russ ,  Jens Schneider

IPC分类号： H01L29/94 ,  H03K3/01

CPC分类号： H01L29/94 ,  H01L27/0811

摘要： A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.

摘要翻译： 公开了一种在n型阱中包括电容器的电路装置。 电容器的特定极化确保在阱中产生耗尽区，并且电容器具有高的ESD强度。 任选地存在的辅助掺杂层确保电容器的高面积电容，尽管具有高的ESD强度。

公开(公告)号：US20080277729A1

公开(公告)日：2008-11-13

申请号：US12176659

申请日：2008-07-21

申请人： Harald Gossner ,  Christian Russ

发明人： Harald Gossner ,  Christian Russ

IPC分类号： H02H9/04 ,  H01L27/06

CPC分类号： H01L27/1211 ,  H01L27/0288 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/8086 ,  H01L2029/7857

摘要： A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

摘要翻译： 在电路中用作静电放电（ESD）保护元件的栅极控制鳍电阻元件具有鳍状结构，其具有形成在第一和第二连接区域之间的第一连接区域，第二连接区域和沟道区域。 此外，散热片电阻元件具有形成在通道区域的表面的至少一部分上的栅极区域。 栅极区域电耦合到栅极控制装置，栅极控制装置控制施加到栅极区域的电位，使得栅极控制的鳍状电阻元件在电路的第一操作状态期间具有高电阻 并且在第二操作状态期间具有较低的电阻，其特征在于发生ESD事件。

公开(公告)号：US07202527B2

公开(公告)日：2007-04-10

申请号：US10903027

申请日：2004-07-29

申请人： Kai Esmark ,  Harald Gossner ,  Gunther Mackh ,  Richard Owen ,  Franz Zängl

发明人： Kai Esmark ,  Harald Gossner ,  Gunther Mackh ,  Richard Owen ,  Franz Zängl

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/7833 ,  H01L29/7836

摘要： A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the drain zone and a substrate region is vertically shifted and a voltage ratio of the MOS transistor between a lateral breakdown voltage and a vertical breakdown voltage can be set.

摘要翻译： MOS晶体管包括漏极区，源极区和栅电极。 第一导电类型的掺杂原子通过至少两个另外的注入步骤注入到漏区和源区的区域中，使得漏区和衬底区之间的pn结垂直移位，MOS的电压比 可以设置横向击穿电压和垂直击穿电压之间的晶体管。

公开(公告)号：US20070040221A1

公开(公告)日：2007-02-22

申请号：US11506683

申请日：2006-08-18

申请人： Harald Gossner ,  Christian Russ

发明人： Harald Gossner ,  Christian Russ

IPC分类号： H01L23/62

CPC分类号： H01L27/1211 ,  H01L27/0288 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/8086 ,  H01L2029/7857

摘要： A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

摘要翻译： 在电路中用作静电放电（ESD）保护元件的栅极控制鳍电阻元件具有鳍状结构，其具有形成在第一和第二连接区域之间的第一连接区域，第二连接区域和沟道区域。 此外，散热片电阻元件具有形成在通道区域的表面的至少一部分上的栅极区域。 栅极区域电耦合到栅极控制装置，栅极控制装置控制施加到栅极区域的电位，使得栅极控制的鳍状电阻元件在电路的第一操作状态期间具有高电阻 并且在第二操作状态期间具有较低的电阻，其特征在于发生ESD事件。

公开(公告)号：US06905892B2

公开(公告)日：2005-06-14

申请号：US10200067

申请日：2002-07-19

申请人： Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

发明人： Kai Esmark ,  Harald Gossner ,  Philipp Riess ,  Wolfgang Stadler ,  Martin Streibl ,  Martin Wendel

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/74 ,  G01R31/26

CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).

摘要翻译： 本发明创造了具有基板的半导体部件的操作方法; 具有施加到衬底的导电多晶硅条; 具有连接到导电多晶硅条的第一和第二电接触，使得它们之间形成电阻; 半导体部件在其具有第一差分电阻（Rdiff 1）的电流/电压范围内可逆地操作，直到对应于上限电压限制值（Vt）的电流限制值（It），并且在当前值更大 具有小于第一差分电阻（Rdiff 1）的第二差分电阻（Rdiff 2）。