公开(公告)号：US5606717A

公开(公告)日：1997-02-25

申请号：US847651

申请日：1992-03-05

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: An interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuit for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets. The computer system has a plurality of semiconductor circuits. The interfacing circuitry is coupled to the multiline bus. The multiline bus has a total number of lines less than a total number of bits in any single address. The interfacing circuitry resides inside the semiconductor circuit and includes a decoder for decoding the packets received to identify the data, addresses, and control information. A control logic circuitry is coupled to the decoder circuitry for controlling device operation of the first semiconductor circuit in accordance with the data, addresses, and control information received. A register circuitry is coupled to the decoder and the control logic circuitry for storing a first value corresponding to a first predetermined time period during which the interfacing circuitry must wait before transmitting reply information through the multiline bus in response to the data, addresses, and control information received. The register circuitry applies the first value to the control logic circuitry to cause the control logic circuitry to wait for the first predetermined time period before accessing the multiline bus for transmitting the reply information.

Abstract translation: 用于计算机系统的半导体电路的接口电路根据从计算机系统的多行总线以分组的形式接收的数据，地址和控制信息来选择用于设备操作的半导体电路。 计算机系统具有多个半导体电路。 接口电路耦合到多线总线。 多行总线的总线数小于任何单个地址中的总位数。 接口电路位于半导体电路内，并且包括用于对接收到的分组进行解码以识别数据，地址和控制信息的解码器。 控制逻辑电路耦合到解码器电路，用于根据所接收的数据，地址和控制信息来控制第一半导体电路的设备操作。 寄存器电路耦合到解码器和控制逻辑电路，用于存储对应于第一预定时间段的第一值，在该第一预定时间段期间，接口电路必须在响应于数据，地址和控制在通过多线总线发送应答信息之前等待 收到的资料 寄存器电路将第一值应用于控制逻辑电路，以使得控制逻辑电路在访问多行总线之前等待第一预定时间段以发送回复信息。

公开(公告)号：US5243703A

公开(公告)日：1993-09-07

申请号：US849211

申请日：1992-03-05

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/006 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108

Abstract: An apparatus for synchronously generating a first clock signal in a first circuitry and a second clock signal in a second circuitry of a data processing system is described. A clock generating circuitry generates a global clock signal. A transmission line transfers the global clock signal from its first end to its second end and includes a midpoint between the first end and the second end. A first clock signal generation circuit is coupled at a first point between the first end and the midpoint and a second point between the midpoint and the second end. The first and second points have the same line length to the midpoint. The first clock signal generation circuit generates the first clock signal at a first timing point which is halfway between the global clock signal with a first propagation delay from the first end to the first point and the signal with a second propagation delay from the first end to the second point. A second clock signal generation circuit is coupled at a third point between the first end and the midpoint and a fourth point between the midpoint and the second end. The third and fourth points have the same line length to the midpoint. The second clock signal generation circuit generates the second clock signal at a second timing point which is halfway between the global clock signal with a third propagation delay from the first end to the third point and the signal with a fourth propagation delay from the first end to the fourth point. The first timing point is the same as the second timing point such that the first signal is synchronized with the second signal.

Abstract translation: 描述了一种在数据处理系统的第二电路中同步产生第一电路中的第一时钟信号和第二时钟信号的装置。 时钟发生电路产生全局时钟信号。 传输线将全局时钟信号从其第一端传送到其第二端，并且包括第一端和第二端之间的中点。 第一时钟信号产生电路在第一端和中点之间的第一点处耦合，并且在中点和第二端之间连接第二点。 第一点和第二点与中点具有相同的线长度。 第一时钟信号产生电路在第一定时点处产生第一时钟信号，该第一定时点位于全局时钟信号之间的第一时钟信号与从第一端到第一点的第一传播延迟，以及从第一端到第二传播延迟的信号 第二点。 第二时钟信号产生电路在第一端和中点之间的第三点耦合，并且在中点和第二端之间连接第四点。 第三点和第四点与中点具有相同的行长度。 第二时钟信号产生电路在第二定时点产生第二时钟信号，该第二定时点位于具有从第一端到第三点的第三传播延迟的全局时钟信号之间的中间，以及从第一端到第四传播延迟的信号 第四点。 第一定时点与第二定时点相同，使得第一信号与第二信号同步。

公开(公告)号：US20050141332A1

公开(公告)日：2005-06-30

申请号：US10973268

申请日：2004-10-27

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 。 本发明还包括用于主设备和从设备在总线上通信的协议，以及用于每个设备中的寄存器以区分每个设备并允许总线请求被引导到单个或所有设备的协议。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

公开(公告)号：US20050030802A1

公开(公告)日：2005-02-10

申请号：US10939501

申请日：2004-09-14

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 。 本发明还包括用于主设备和从设备在总线上通信的协议，以及用于每个设备中的寄存器以区分每个设备并允许总线请求被引导到单个或所有设备的协议。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

公开(公告)号：US06715020B2

公开(公告)日：2004-03-30

申请号：US10037171

申请日：2001-12-21

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C800

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108

Abstract: A controller device for controlling a synchronous dynamic random access memory device. The controller device includes output driver circuitry to output block size information to the memory device. The block size information defines an amount of data to be output by the memory device. In addition, the controller device includes input receiver circuitry to receive the amount of data output by the memory device.

Abstract translation: 一种用于控制同步动态随机存取存储器件的控制器装置。 控制器设备包括输出驱动器电路，以将块大小信息输出到存储器件。 块大小信息定义要由存储器件输出的数据量。 此外，控制器设备包括输入接收器电路，用于接收由存储器件输出的数据量。

公开(公告)号：US06570814B2

公开(公告)日：2003-05-27

申请号：US09893836

申请日：2001-06-28

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C700

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated circuit device which includes an array of dynamic memory cells. The integrated circuit device comprises an input receiver to sample an operation code synchronously with respect to a transition of a clock signal, the operation code indicating a read operation. The integrated circuit device also comprises an output driver to output data in response to the operation code, wherein the data is output after a number of clock cycles of the clock signal transpire.

Abstract translation: 一种包括动态存储单元阵列的集成电路装置。 集成电路装置包括输入接收器，用于相对于时钟信号的转换同步地对操作代码进行采样，所述操作代码指示读取操作。 集成电路装置还包括响应于操作码输出数据的输出驱动器，其中在时钟信号的数个时钟周期发生之后输出数据。

公开(公告)号：US06564281B2

公开(公告)日：2003-05-13

申请号：US09969489

申请日：2001-10-01

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1300

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A synchronous memory device including an array of memory cells. The memory device includes a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. The memory device further includes input receiver circuitry to sample an operation code synchronously with respect to a transition of an external clock signal. The operation code including precharge information and, in response to the precharge information, the plurality of sense amplifiers are automatically precharged after the data is sensed.

Abstract translation: 一种包括存储器单元阵列的同步存储器件。 存储器件包括耦合到存储器单元阵列的多个读出放大器以感测数据。 存储器件还包括输入接收器电路，用于相对于外部时钟信号的转换同步地对操作代码进行采样。 在检测到数据之后，包括预充电信息和响应于预充电信息的多个读出放大器的操作代码被自动预充电。

公开(公告)号：US06426916B2

公开(公告)日：2002-07-30

申请号：US09796206

申请日：2001-02-27

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C300

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14

Abstract: A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing a value which is representative of a number of cycles of an external clock signal to transpire after which the memory device responds to a read request. The method further includes providing block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes receiving the amount of data, after the number of clock cycles of the external clock signal transpire.

Abstract translation: 一种同步存储装置及其操作和控制方法。 控制存储器件的方法包括提供表示外部时钟信号的周期数的值，在此之后存储器件响应于读取请求。 该方法还包括向存储器件提供块大小信息，其中块大小信息定义响应于读取请求由存储器件输出的数据量。 该方法还包括在外部时钟信号的时钟周期数量发生之后接收数据量。

公开(公告)号：US06415339B1

公开(公告)日：2002-07-02

申请号：US09221108

申请日：1998-12-28

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1328

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A synchronous memory device and a method of controlling the memory device. The memory device including at least one memory section having a plurality of memory cells. The memory device includes a first internal register to store a value which is indicative of a number of clock cycles to transpire before the memory device responds to a read request. The memory device also includes a second internal register to store an identification value to identify the memory device on a bus.

Abstract translation: 一种同步存储装置和一种控制存储装置的方法。 所述存储装置包括至少一个具有多个存储单元的存储器部分。 存储器件包括第一内部寄存器，用于存储指示在存储器件响应于读取请求之前要发生的时钟周期数的值。 存储器件还包括第二内部寄存器，用于存储识别值以识别总线上的存储器件。

公开(公告)号：US06314051B1

公开(公告)日：2001-11-06

申请号：US09629497

申请日：2000-07-31

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C800

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to a write request, a first portion of data after a number of clock cycles of the external clock signal transpire. The first portion of data is sampled synchronously with respect to the external clock signal.

Abstract translation: 一种具有多个存储器单元的存储器件，所述存储器件包括用于接收外部时钟信号的时钟接收器电路，以及输入接收器电路，以响应于写入请求，在多个时钟周期之后采样数据的第一部分 外部时钟信号发出。 数据的第一部分相对于外部时钟信号被同步采样。