公开(公告)号：US20080256551A1

公开(公告)日：2008-10-16

申请号：US12067587

申请日：2005-09-21

申请人： Michael Priel ,  Dan Kuzmin ,  Leonid Smolyansky

发明人： Michael Priel ,  Dan Kuzmin ,  Leonid Smolyansky

IPC分类号： G06F9/46

CPC分类号： G06F9/462

摘要： A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.

摘要翻译： 一种用于存储状态信息的方法，所述方法包括在第一电路处存储表示第二电路的状态的状态信息，同时第二电路进入低功率模式; 其特征在于接收从第一任务切换到第二任务的任务应发生的指示; 在所述第一电路处存储表示所述第二电路的状态的状态信息; 收到第一个任务应恢复的指示; 以及将所存储的状态信息从第一电路写入第二电路。 一种系统包括第一电路和第二电路，而第一电路连接到第二电路，并适于存储表示第二电路的状态的状态信息; 其特征在于包括控制器，其适于在所述第二电路的至少一部分断电或者所述第二电路与任务切换操作相关联时控制所述状态信息的存储。

公开(公告)号：US09766651B2

公开(公告)日：2017-09-19

申请号：US14651279

申请日：2013-01-08

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： G05F1/10 ,  G06F1/10 ,  H03K3/012 ,  H03L7/099 ,  H03L7/097 ,  H03L7/08 ,  G06F1/12

CPC分类号： G06F1/10 ,  G06F1/12 ,  H03K3/012 ,  H03L7/08 ,  H03L7/097 ,  H03L7/099 ,  H03L7/0992

摘要： The present invention provides a clock source for an integrated circuit, comprising a primary oscillator adapted to generate a primary clock signal based on a reference control signal, at least one secondary oscillator each secondary oscillator being adapted to generate a secondary clock signal based on the reference control signal, wherein for each secondary oscillator a frequency correction unit is provided and adapted to adjust the reference control signal for the associated secondary oscillator based on the primary clock signal and the secondary clock signal of the associated secondary oscillator such that the clock frequency of the secondary clock signal of the associated secondary oscillator essentially equals the clock frequency of the primary clock signal. The present invention furthermore provides a method for providing a clock signal, and an integrated circuit.

公开(公告)号：US09337717B2

公开(公告)日：2016-05-10

申请号：US14415611

申请日：2012-07-19

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： H02M1/15 ,  G05F1/613 ,  G06F1/26 ,  H01L23/60

CPC分类号： H02M1/15 ,  G05F1/613 ,  G06F1/26 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus for voltage ripple reduction on a power supply line of an integrated circuit device is provided to be operable in at least two modes. The apparatus includes: one or more clamping devices connectable to the power supply line; a clamp control unit; and a mode change detection unit arranged to monitor an interface of the integrated circuit device for one or more information indicating an upcoming mode change of the integrated circuit device and to provide a mode change signal to the clamp control unit when the one or more information is detected. The clamp control unit is arranged to connect at least one of the one or more clamping devices to the power supply line when receiving the mode change signal.

摘要翻译： 提供了一种用于集成电路器件的电源线上的电压纹波降低的装置，以至少两种模式可操作。 该装置包括：可连接到电源线的一个或多个夹紧装置; 夹具控制单元; 以及模式改变检测单元，被配置为监视集成电路装置的接口，用于指示集成电路装置的即将到来的模式改变的一个或多个信息，并且当所述一个或多个信息是 检测到。 钳位控制单元被布置成当接收到模式改变信号时，将一个或多个钳位装置中的至少一个连接到电源线。

公开(公告)号：US09214924B2

公开(公告)日：2015-12-15

申请号：US14006388

申请日：2011-03-25

申请人： Michael Priel ,  Dan Kuzmin ,  Yossi Shoshany

发明人： Michael Priel ,  Dan Kuzmin ,  Yossi Shoshany

IPC分类号： H03K3/011 ,  H03K19/003

CPC分类号： H03K3/011 ,  H03K19/00346

摘要： An integrated circuit is provided that includes a plurality of modules comprising at least one clock-gated module and a controller unit, which is arranged to enable and disable provision of a clock signal to the at least one clock-gated module. The at least one clock-gated module includes one or more electronic circuits arranged to be in a first state of an electrical stress condition during a first portion of a period of time and in a second state of less electrical stress than in the first state during a second portion of the period of time. The at least one clock-gated module is further arranged to switch the one or more electronic circuits between the first state and the second state such that a change of a characteristic of at least one of the one or more electronic circuits caused by the electrical stress condition is at least partially reduced.

摘要翻译： 提供了一种集成电路，其包括多个模块，所述多个模块包括至少一个时钟门控模块和控制器单元，所述控制器单元被布置成使能和禁止向所述至少一个时钟门控模块提供时钟信号。 所述至少一个时钟门控模块包括一个或多个电子电路，其布置成在一段时间段的第一部分期间处于电应力状态的第一状态，并且处于比在第一状态期间小的电应力的第二状态 这段时间的第二部分。 所述至少一个时钟选通模块还被布置成在所述第一状态和所述第二状态之间切换所述一个或多个电子电路，使得由所述电应力引起的所述一个或多个电子电路中的至少一个的特性的改变 条件至少部分减少。

公开(公告)号：US20150180475A1

公开(公告)日：2015-06-25

申请号：US14409310

申请日：2012-07-06

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： H03K19/0175

CPC分类号： H03K19/017509 ,  H03K19/00384 ,  H03K19/018521

摘要： An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.

摘要翻译： 描述了一个输入/输出（IO）驱动电路。 IO缓冲器驱动器电路包括：用于接收输入信号的至少一个输入和用于提供至少一个输出信号的至少一个输出; 以及多个开关，被布置成向所述至少一个输出端提供低电压值和高电压值之间的可变电压电平。 多个开关中的至少一个第一开关被布置成在第一时间段内启动电压变化到低电压值和高电压值之间的中间电压电平。 多个开关中的至少一个第二开关被布置成在第二时间段内将电压变化继续到低电压值或高电压值。

公开(公告)号：US20140325183A1

公开(公告)日：2014-10-30

申请号：US14358053

申请日：2011-11-28

申请人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel ,  Leonid Smolyansky

发明人： Anton Rozen ,  Dan Kuzmin ,  Michael Priel ,  Leonid Smolyansky

IPC分类号： G06F15/76

CPC分类号： G06F15/76 ,  G06F9/5083 ,  G06F9/5094 ,  G06F2015/765 ,  Y02D10/22

摘要： An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.

摘要翻译： 描述了一种非对称多核处理模块。 非对称多核处理模块包括至少一个第一类型的处理核心，至少一个另外类型的至少一个处理核心和至少一个核心标识符配置组件。 至少一个核心标识符配置组件被布置成使得能够动态地配置第一和至少一个其它类型的至少一个处理核心的核心标识符的值。

公开(公告)号：US08402288B2

公开(公告)日：2013-03-19

申请号：US11719015

申请日：2004-11-10

申请人： Anton Rozen ,  Michael Priel ,  Dan Kuzmin

发明人： Anton Rozen ,  Michael Priel ,  Dan Kuzmin

IPC分类号： G06F1/00 ,  G06F17/50 ,  G05F1/10 ,  G05F3/02 ,  G06G7/48 ,  G06G7/62

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The method comprises: providing at least one reference circuit representative of a behavior of at least one estimated circuit, whereas the at least one estimated circuit includes transistors of multiple types; supplying at least one input signal to at least one reference circuits and monitoring a behavior of the at least one reference circuit one or more reference circuit; determining a characteristic of at least one output signal provided to the at least one estimated circuit; and providing at least one output signal to one or more estimated circuitsThe apparatus includes at least one reference circuit representative of a behavior of at least one estimated circuit, whereas the at least one estimated circuit includes transistors of multiple types; and monitoring circuitry adapted to monitor a behavior of at least one reference circuit and to determine a characteristic of at least one output signal provided to the at least one estimated circuit.

摘要翻译： 一种用于控制提供给系统的电压电平和时钟信号频率的方法和装置。 该方法包括：提供代表至少一个估计电路的行为的至少一个参考电路，而至少一个估计电路包括多种类型的晶体管; 向至少一个参考电路提供至少一个输入信号并监视所述至少一个参考电路的行为一个或多个参考电路; 确定提供给所述至少一个估计电路的至少一个输出信号的特性; 并且向一个或多个估计电路提供至少一个输出信号。所述装置包括表示至少一个估计电路的行为的至少一个参考电路，而所述至少一个估计电路包括多种类型的晶体管; 以及监视电路，其适于监视至少一个参考电路的行为并且确定提供给所述至少一个估计电路的至少一个输出信号的特性。

公开(公告)号：US20130007431A1

公开(公告)日：2013-01-03

申请号：US13582769

申请日：2010-03-22

申请人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

发明人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

IPC分类号： G06F9/00 ,  G06F1/32

CPC分类号： H04W52/0261 ,  G06F1/32 ,  G06F9/00 ,  Y02D70/00

摘要： An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process.

摘要翻译： 集成电路装置包括信号处理系统，该信号处理系统具有通过第一生产过程制造的至少一个第一信号处理模块; 以及通过第二生产过程制造的至少一个第二信号处理模块，其中第二生产过程与第一生产过程不同。 信号处理系统还包括信号处理管理模块，其被布置成：确定集成电路装置的期望的系统性能; 确定信号处理系统的至少一个操作条件; 并且至少部分地基于：确定的期望系统性能来配置所述信号处理系统的信号处理操作模式; 所述至少一个确定的操作条件; 以及第一生产过程和第二生产过程中的至少一个。

公开(公告)号：US08171336B2

公开(公告)日：2012-05-01

申请号：US12163610

申请日：2008-06-27

申请人： Michael Priel ,  Dan Kuzmin ,  Amir Zaltzman

发明人： Michael Priel ,  Dan Kuzmin ,  Amir Zaltzman

IPC分类号： G06F1/14 ,  G06F1/32 ,  G06F13/10 ,  G06F21/22

CPC分类号： G06F1/14 ,  G06F21/71 ,  G06F21/81

摘要： A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower than the high frequency of the predefined high frequency code.

摘要翻译： 一种用于保护安全实时时钟模块的方法，所述方法包括：如果所述安全实时时钟模块的多个输入端口在至少第一持续时间内空闲，则锁定所述安全实时时钟模块的多个输入端口; 如果在所述安全实时时钟模块的控制输入端口上接收到预定义的高频码，则解锁所述安全实时时钟模块的多个输入端口; 以及当所述安全实时时钟模块的多个输入端口被锁定时以及当所述安全实时时钟模块的所述多个输入端口被解锁时，提供安全的实时时钟信号; 其中电源电压的变化导致供电电压引起提供给安全实时时钟模块的输入端口的输入信号的变化; 其中，所述输入信号的所述电源电压的感应变化的最大频率低于所述预定的高频码的高频。

公开(公告)号：US08060324B2

公开(公告)日：2011-11-15

申请号：US12162179

申请日：2006-02-01

申请人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

发明人： Michael Priel ,  Dan Kuzmin ,  Anton Rozen

IPC分类号： G01R11/073 ,  G01R11/20 ,  G01R19/165 ,  G06F11/07

CPC分类号： G01R31/27 ,  G01R31/2882

摘要： A method and a device for estimating parameter variations of transistors that belong to the same circuit. The method includes: providing the first circuit; providing a test circuit adapted to perform a first function and a stacked test circuit adapted to perform a second function that substantially equals the first function; wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions; determining a relationship between a parameter of the test circuit and a parameter of the stacked test circuit; and estimating parameter variations of transistors that belong to the first circuit in response to the determined relationship.

摘要翻译： 一种用于估计属于相同电路的晶体管的参数变化的方法和装置。 该方法包括：提供第一电路; 提供适于执行第一功能的测试电路和适于执行基本上等于所述第一功能的第二功能的堆叠测试电路; 其中所述测试电路，所述堆叠测试电路和所述第一电路在基本相同的处理条件下进行处理; 确定所述测试电路的参数与所述堆叠测试电路的参数之间的关系; 以及响应于所确定的关系估计属于所述第一电路的晶体管的参数变化。