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公开(公告)号：US20150134932A1
公开(公告)日：2015-05-14
申请号：US13977152
申请日：2011-12-30
Applicant: Cameron B. Mcnairy
Inventor： Cameron B. Mcnairy
CPC classification number: G06F15/76 , G06F9/3004 , G06F9/30047 , G06F9/30076 , G06F9/30105 , G06F9/3824 , G06F11/1064 , G06F12/0842 , G06F12/0846 , G06F12/0875 , G06F2015/765 , G06F2212/452
Abstract: A method of an aspect, which may be performed responsive to one or more structure access instructions, includes changing a state of a portion of a structure of a processor to a sequestered state. In the sequestered state, components of the processor are not able to access the portion of the structure but are able to access one or more other portions of the structure. Non-architecturally visible data in the portion of the structure is modified, while the portion of the structure is in the sequestered state. The state of the portion of the structure is then changed from the sequestered state to a non-sequestered state, after the non-architecturally visible data in the portion of the structure has been modified. Other methods, apparatus, systems, and instructions are also disclosed.
Abstract translation: 可以响应于一个或多个结构访问指令执行的方面的方法包括将处理器的结构的一部分的状态改变为隔离状态。 在隔离状态下，处理器的组件不能访问结构的部分，但是能够访问结构的一个或多个其他部分。 在结构部分中的非结构可视数据被修改，而结构的部分处于隔离状态。 然后在结构部分中的非结构化可视数据已被修改之后，结构部分的状态从隔离状态改变为非隔离状态。 还公开了其它方法，装置，系统和指令。
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公开(公告)号：US20110040848A1
公开(公告)日：2011-02-17
申请号：US12542144
申请日：2009-08-17
Applicant: Zhichen Xu
Inventor： Zhichen Xu
IPC: G06F17/30 , G06F15/167
CPC classification number: H04L67/32 , G06F12/0868 , G06F2015/765 , G06Q50/01 , H04L67/26 , H04L67/2842 , H04L67/306 , H04L67/325
Abstract: Embodiments are directed towards modifying a distribution of writers as either a push writer or a pull writer based on a cost model that decides for a given content reader whether it is more effective for the writer to be a pull writer or a push writer. A cache is maintained for each content reader for caching content items pushed by a push writer in the content writer's push list of writers when the content is generated. At query time, content items are pulled by the content reader based on writers a content reader's pull list. One embodiment of the cost model employs data about a previous number of requests for content items for a given writer for a number of previous blended display results of content items. When a writer is determined to be popular, mechanisms are proposed for pushing content items to a plurality of content readers.
Abstract translation: 实施例旨在基于决定给定内容读取器的成本模型来将作者的分布修改为推送写入器或拉写入器，以使作者是更有效的作为拉写入器还是推动写入器。 为每个内容读取器维护高速缓存，用于在生成内容时缓存内容写入者的推送列表中的推送写入器推送的内容项目。 在查询时，内容读取器根据写入者提取内容读取器的列表。 成本模型的一个实施例使用关于给定写入器的先前数量的内容项的请求的数据用于多个内容项的先前混合显示结果。 当作者被确定为流行时，提出将内容项推送到多个内容阅读器的机制。
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3.发明申请INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR 审中-公开集成电路设备，不对称多核处理模块，电子设备及其计算机程序代码的执行方法公开(公告)号：US20140325183A1
公开(公告)日：2014-10-30
申请号：US14358053
申请日：2011-11-28
Applicant: Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
Inventor： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
IPC: G06F15/76
CPC classification number: G06F15/76 , G06F9/5083 , G06F9/5094 , G06F2015/765 , Y02D10/22
Abstract: An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.
Abstract translation: 描述了一种非对称多核处理模块。 非对称多核处理模块包括至少一个第一类型的处理核心，至少一个另外类型的至少一个处理核心和至少一个核心标识符配置组件。 至少一个核心标识符配置组件被布置成使得能够动态地配置第一和至少一个其它类型的至少一个处理核心的核心标识符的值。
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公开(公告)号：US20140136595A1
公开(公告)日：2014-05-15
申请号：US14157867
申请日：2014-01-17
Applicant: YAHOO! INC.
Inventor： Zhichen Xu
IPC: H04L29/08
CPC classification number: H04L67/32 , G06F12/0868 , G06F2015/765 , G06Q50/01 , H04L67/26 , H04L67/2842 , H04L67/306 , H04L67/325
Abstract: Embodiments are directed towards modifying a distribution of writers as either a push writer or a pull writer based on a cost model that decides for a given content reader whether it is more effective for the writer to be a pull writer or a push writer. A cache is maintained for each content reader for caching content items pushed by a push writer in the content writer's push list of writers when the content is generated. At query time, content items are pulled by the content reader based on writers a content reader's pull list. One embodiment of the cost model employs data about a previous number of requests for content items for a given writer for a number of previous blended display results of content items. When a writer is determined to be popular, mechanisms are proposed for pushing content items to a plurality of content readers.
Abstract translation: 实施例旨在基于决定给定内容读取器的成本模型来将作者的分布修改为推送写入器或拉写入器，以使作者是更有效的作为拉写入器还是推动写入器。 为每个内容读取器维护高速缓存，用于在生成内容时缓存内容写入者的推送列表中的推送写入器推送的内容项目。 在查询时，内容读取器根据写入者提取内容读取器的列表。 成本模型的一个实施例使用关于给定写入器的先前数量的内容项的请求的数据用于多个内容项的先前混合显示结果。 当作者被确定为流行时，提出将内容项推送到多个内容阅读器的机制。
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公开(公告)号：US12013810B2
公开(公告)日：2024-06-18
申请号：US17956013
申请日：2022-09-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Matthaeus G. Chajdas
CPC classification number: G06F15/80 , G06T15/005 , G06F2015/765
Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.
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Patent Agency Ranking
公开(公告)号：US08655842B2
公开(公告)日：2014-02-18
申请号：US12542144
申请日：2009-08-17
Applicant: Zhichen Xu
Inventor： Zhichen Xu
IPC: G06F17/30
CPC classification number: H04L67/32 , G06F12/0868 , G06F2015/765 , G06Q50/01 , H04L67/26 , H04L67/2842 , H04L67/306 , H04L67/325
Abstract: Embodiments are directed towards modifying a distribution of writers as either a push writer or a pull writer based on a cost model that decides for a given content reader whether it is more effective for the writer to be a pull writer or a push writer. A cache is maintained for each content reader for caching content items pushed by a push writer in the content writer's push list of writers when the content is generated. At query time, content items are pulled by the content reader based on writers a content reader's pull list. One embodiment of the cost model employs data about a previous number of requests for content items for a given writer for a number of previous blended display results of content items. When a writer is determined to be popular, mechanisms are proposed for pushing content items to a plurality of content readers.
Abstract translation: 实施例旨在基于决定给定内容读取器的成本模型来将作者的分布修改为推送写入器或拉写入器，以使作者是更有效的作为拉写入器还是推动写入器。 为每个内容读取器维护高速缓存，用于在生成内容时缓存内容写入者的推送列表中的推送写入器推送的内容项目。 在查询时，内容读取器根据写入者提取内容读取器的列表。 成本模型的一个实施例使用关于给定写入器的先前数量的内容项的请求的数据用于多个内容项的先前混合显示结果。 当作者被确定为流行时，提出将内容项推送到多个内容阅读器的机制。
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公开(公告)号：US20240143457A1
公开(公告)日：2024-05-02
申请号：US18406346
申请日：2024-01-08
Applicant: NeuroBlade Ltd.
Inventor： Elad SITY , Eliad HILLEL
IPC: G06F11/16 , G06F9/30 , G06F9/38 , G06F11/10 , G06F13/16 , G06F15/80 , G06N3/04 , G11C7/10 , G11C11/16 , G11C11/4076 , G11C11/408 , G11C11/4093
CPC classification number: G06F11/1658 , G06F9/3001 , G06F9/3885 , G06F9/3889 , G06F9/3895 , G06F11/1016 , G06F11/102 , G06F11/16 , G06F11/1616 , G06F13/1657 , G06F15/8038 , G06N3/04 , G11C7/1072 , G11C11/1655 , G11C11/1657 , G11C11/1675 , G11C11/4076 , G11C11/408 , G11C11/4093 , G06F2015/765
Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.
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公开(公告)号：US20240111710A1
公开(公告)日：2024-04-04
申请号：US17956013
申请日：2022-09-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Matthaeus G. Chajdas
CPC classification number: G06F15/80 , G06T15/005 , G06F2015/765
Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.
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公开(公告)号：US11914487B2
公开(公告)日：2024-02-27
申请号：US17397061
申请日：2021-08-09
Applicant: NeuroBlade, Ltd.
Inventor： Elad Sity , Eliad Hillel
IPC: G06F11/16 , G06F9/38 , G06F13/16 , G06F15/80 , G11C7/10 , G11C11/4076 , G11C11/16 , G11C11/408 , G06F9/30 , G06N3/04 , G06F11/10 , G11C11/4093 , G06F15/76
CPC classification number: G06F11/1658 , G06F9/3001 , G06F9/3885 , G06F9/3889 , G06F9/3895 , G06F11/102 , G06F11/1016 , G06F11/16 , G06F11/1616 , G06F13/1657 , G06F15/8038 , G06N3/04 , G11C7/1072 , G11C11/1655 , G11C11/1657 , G11C11/1675 , G11C11/408 , G11C11/4076 , G11C11/4093 , G06F2015/765
Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.
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公开(公告)号：US09772971B2
公开(公告)日：2017-09-26
申请号：US14400401
申请日：2013-05-23
Applicant: Roger A. Smith
Inventor： Roger A. Smith
CPC classification number: G06F15/825 , G06F7/76 , G06F11/00 , G06F11/1484 , G06F11/2002 , G06F12/0875 , G06F15/76 , G06F2015/765 , G06F2212/452
Abstract: A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain (MM domain) which includes mentor processors for mentoring the DID according to “meta information” which includes but is not limited to data, algorithms and protective rule sets. The term “mentoring” (as defined herein below) refers to, among other things, applying and using meta information to enforce rule sets and/or dynamically erecting abstractions and virtualizations by which resources in the DID are shuffled around for, inter alia, efficiency and fault correction. Meta Mentor processors create systems and sub-systems by means of fault tolerant mentor switches that route signals to and from hardware and software entities. The systems and sub-systems created are distinct sub-architectures and unique configurations that may be operated as separately or concurrently as defined by the executing processes.
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