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    CROSSTALK CANCELLATION FOR SIGNAL LINES
    43.
    发明申请
    CROSSTALK CANCELLATION FOR SIGNAL LINES 有权

    公开(公告)号：US20220346220A1

    公开(公告)日：2022-10-27

    申请号：US17238797

    申请日：2021-04-23

    Applicant: Micron Technology, Inc.

    Inventor： M. Ataul Karim ,  David K. Ovard ,  Aparna U. Limaye ,  Timothy M. Hollis

    IPC: H05K1/02 ,  H04B3/487 ,  H04B3/32

    Abstract: Methods, systems, and devices for crosstalk cancellation for signal lines are described. In some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. The device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. The device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.

    SEQUENTIAL SLC READ OPTIMIZATION
    45.
    发明申请
    SEQUENTIAL SLC READ OPTIMIZATION 有权

    公开(公告)号：US20220172769A1

    公开(公告)日：2022-06-02

    申请号：US17673302

    申请日：2022-02-16

    Applicant: Micron Technology, Inc.

    Inventor： Tomoko Ogura Iwasaki ,  Tracy D. Evans ,  Avani F. Trivedi ,  Aparna U. Limaye ,  Jianmin Huang

    IPC: G11C11/408 ,  G06F12/02 ,  G11C11/4074

    Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.

    Sequential SLC read optimization
    46.
    发明授权
    Sequential SLC read optimization 有权

    公开(公告)号：US11282567B2

    公开(公告)日：2022-03-22

    申请号：US16947795

    申请日：2020-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Tomoko Ogura Iwasaki ,  Tracy D. Evans ,  Avani F. Trivedi ,  Aparna U. Limaye ,  Jianmin Huang

    IPC: G11C11/408 ,  G06F12/02 ,  G11C11/4074

    Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.

    SEMICONDUCTOR PACKAGES AND ASSOCIATED METHODS WITH ANTENNAS AND EMI ISOLATION SHIELDS
    48.
    发明申请
    SEMICONDUCTOR PACKAGES AND ASSOCIATED METHODS WITH ANTENNAS AND EMI ISOLATION SHIELDS 有权

    公开(公告)号：US20220068837A1

    公开(公告)日：2022-03-03

    申请号：US17524473

    申请日：2021-11-11

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Dong Soon Lim ,  Randon K. Richards ,  Aparna U. Limaye

    IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01Q1/22

    Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure. In some embodiments, the semiconductor device includes a package molding over at least a portion of the antenna, the EMI shield, and/or the second dielectric material.

    RESPONDING TO CHANGES IN AVAILABLE POWER SUPPLY
    49.
    发明申请
    RESPONDING TO CHANGES IN AVAILABLE POWER SUPPLY 有权

    公开(公告)号：US20210202017A1

    公开(公告)日：2021-07-01

    申请号：US17200959

    申请日：2021-03-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Avani F. Trivedi ,  Tracy D. Evans ,  Carla L. Christensen ,  Tomoko Ogura Iwasaki ,  Aparna U. Limaye

    IPC: G11C16/30 ,  G06F13/16 ,  G11C16/10

    Abstract: Memories having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, and a controller configured to cause the memory to determine whether a value of an indication of available power of a power supply for the memory is less than a threshold, and in response to determining that the value of the indication of available power is less than the threshold, increase a size of the first pool of memory cells, limit programming of data received by the memory to the first pool of memory cells, and cease movement of data from the first pool of memory cells to the second pool of memory cells, as well as apparatus including similar memories.

    GARBAGE COLLECTION IN A MEMORY COMPONENT USING AN ADJUSTED PARAMETER
    50.
    发明申请
    GARBAGE COLLECTION IN A MEMORY COMPONENT USING AN ADJUSTED PARAMETER 有权

    公开(公告)号：US20210064265A1

    公开(公告)日：2021-03-04

    申请号：US16995345

    申请日：2020-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Jianmin Huang ,  Aparna U. Limaye ,  Avani F. Trivedi ,  Tomoko Ogura Iwasaki ,  Tracy D. Evans

    IPC: G06F3/06 ,  G06F12/10 ,  G11C16/24 ,  G11C16/34

    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.

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