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    Semiconductor devices with flexible reinforcement structure
    45.
    发明授权
    Semiconductor devices with flexible reinforcement structure 有权

    公开(公告)号：US11574820B2

    公开(公告)日：2023-02-07

    申请号：US16896043

    申请日：2020-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Owen R. Fay ,  Chan H. Yoo

    IPC: H01L21/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31

    Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface connected to the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 μm. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.

    Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer
    47.
    发明授权
    Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer 有权

    公开(公告)号：US11410981B2

    公开(公告)日：2022-08-09

    申请号：US17087043

    申请日：2020-11-02

    Applicant: Micron technology, inc.

    Inventor： Chan H. Yoo ,  Owen R. Fay

    IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

    Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

    MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT
    49.
    发明申请
    MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT 有权

    公开(公告)号：US20210367057A1

    公开(公告)日：2021-11-25

    申请号：US17391920

    申请日：2021-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Thomas H. Kinsley ,  Randon K. Richards

    IPC: H01L29/66 ,  H01L23/495 ,  H05K1/11 ,  H01L23/14 ,  H05K1/18

    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

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