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公开(公告)号：US09508409B2
公开(公告)日：2016-11-29
申请号：US14254378
申请日：2014-04-16
Applicant: Micron Technology, Inc.
Inventor： Mark K. Hadrick , Jeffrey P. Wright , Victor Wong , Simon J. Lovett , Donald M. Morgan , William F. Jones , Sujeet Ayyapureddi , Dean D. Gans , Jongtae Kwak
CPC classification number: G11C7/22 , G11C7/1009 , G11C7/1042 , G11C8/12 , G11C2207/229
Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.
Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。
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公开(公告)号：US09218239B2
公开(公告)日：2015-12-22
申请号：US13917431
申请日：2013-06-13
Applicant: Micron Technology, Inc.
Inventor： Donald M. Morgan
IPC: G06F11/10
CPC classification number: G06F11/10
Abstract: This disclosure relates to error correction circuitry. In one aspect, an error correction circuit can serially receive a digit stream and parse the digit stream into substrings of a predetermined length of digits. Each of the substrings can include data digits and parity digits in certain embodiments. As the substring is received, parity can be tracked in defined regions of the substring. When the entire substring has been received, an error in one of the data digits of the substring can be corrected based on an indication of parity in at least one defined region in some embodiments. Then corrected data, which can include the corrected data digit and the other data digits of the substring, can be stored. According to certain embodiments, the error correction circuit can be implemented by asynchronous circuitry.
Abstract translation: 本发明涉及纠错电路。 在一个方面，纠错电路可以串行地接收数字流并将数字流解析成预定长度的数字的子串。 在某些实施例中，每个子串可以包括数据位和奇数位。 在接收到子字符串时，可以在子字符串的定义区域中跟踪奇偶校验。 当已经接收到整个子串时，在一些实施例中，可以基于在至少一个限定区域中的奇偶校验的指示来校正子串的数据位之一中的错误。 然后可以存储可以包括校正数据数字和子串的其他数据位的校正数据。 根据某些实施例，纠错电路可以由异步电路来实现。
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公开(公告)号：US20130272079A1
公开(公告)日：2013-10-17
申请号：US13915351
申请日：2013-06-11
Applicant: Micron Technology, Inc.
Inventor： Donald M. Morgan
CPC classification number: G11C8/18 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C2207/2272 , H03H11/26
Abstract: Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required.
Abstract translation: 描述了命令延迟系统和方法的示例。 在一些示例中，存储与接收到的命令信号相关联的相位信息，接收的命令信号通过减法时钟触发器流水线传播，并且延迟的命令信号与存储的相位信息组合。 缩小时钟触发器管线可以使用具有比用于发出命令信号的频率更低的频率的时钟。 因此，可能需要较少的触发器。
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公开(公告)号：US20240370176A1
公开(公告)日：2024-11-07
申请号：US18653300
申请日：2024-05-02
Applicant: Micron Technology, Inc.
Inventor： Bryan D. Kerstetter , Alan J. Wilson , Donald M. Morgan
IPC: G06F3/06
Abstract: Systems, methods, and apparatuses are provided for wear leveling repair in a memory device. A host is configured to issue a wear leveling command and a repair request to a memory device configured to check source data in a memory of the memory device for errors in response to receiving the wear leveling command from the host, transfer source data in the memory of the memory device to a target page, and repair a source page if the source data includes an error. The memory device is further configured to set a new repair match if a wear leveling repair element was not consumed after receiving the repair request and flush a previous repair match before setting the new repair match if the wear leveling repair element was consumed and a physical address of an incoming repair request is associated with the wear leveling repair element.
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公开(公告)号：US20240363192A1
公开(公告)日：2024-10-31
申请号：US18761619
申请日：2024-07-02
Applicant: Micron Technology, Inc.
Inventor： Alan John Wilson , Donald M. Morgan , John David Porter
CPC classification number: G11C29/76 , G11C29/54 , G11C29/808
Abstract: Apparatus and methods for page-based soft post package repair are disclosed. Based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. A match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. A decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. A page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.
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Patent Agency Ranking
公开(公告)号：US12086449B1
公开(公告)日：2024-09-10
申请号：US17983213
申请日：2022-11-08
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald M. Morgan
CPC classification number: G06F3/0647 , G06F3/0616 , G06F3/0659 , G06F3/0673 , G06F12/10 , G06F2212/657
Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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公开(公告)号：US20240281368A1
公开(公告)日：2024-08-22
申请号：US18439437
申请日：2024-02-12
Applicant: Micron Technology, Inc.
Inventor： Bryan D. Kerstetter , Donald M. Morgan
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7211
Abstract: Systems, methods, and apparatuses are provided for periodic and activity-based memory management. A memory management bank can be coupled to a memory management block, wherein the memory management bank includes a plurality of memory banks. Each memory bank of the plurality of memory banks includes an activate counter to increment responsive to the memory bank receiving an activate command and circuitry to determine whether a value of the activate counter is equal to or greater than a wear leveling threshold and perform a wear leveling operation on data stored in the memory bank responsive to determining the value of the activate counter is equal to or greater than the wear leveling threshold.
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公开(公告)号：US20230350574A1
公开(公告)日：2023-11-02
申请号：US17731100
申请日：2022-04-27
Applicant: Micron Technology, Inc.
Inventor： Bryan David Kerstetter , Donald M. Morgan , Alan J. Wilson , John David Porter , Jeffrey P. Wright
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F3/0676
Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
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公开(公告)号：US20230116534A1
公开(公告)日：2023-04-13
申请号：US17450582
申请日：2021-10-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Donald M. Morgan , Alan J. Wilson , Bryan D. Kerstetter , John D. Porter
IPC: G11C29/00
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.
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公开(公告)号：US11507296B2
公开(公告)日：2022-11-22
申请号：US17197733
申请日：2021-03-10
Applicant: Micron Technology, Inc.
Inventor： Alan J. Wilson , Donald M. Morgan
Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
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