公开(公告)号：US10141259B1

公开(公告)日：2018-11-27

申请号：US15852339

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H05K1/11 ,  H01L23/528 ,  H01L23/532

Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.

公开(公告)号：US11749608B2

公开(公告)日：2023-09-05

申请号：US17076602

申请日：2020-10-21

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L23/538 ,  H01L23/532 ,  H01L25/11

CPC classification number: H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/53233 ,  H01L23/53261 ,  H01L23/53276 ,  H01L25/117

Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 μm). Adjacent passivation material may also be thin (e.g., less than about 0.2 μm). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.

公开(公告)号：US20230065248A1

公开(公告)日：2023-03-02

申请号：US17820199

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Eiichi Nakano ,  Ying Ta Chiu

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor device assembly including a first semiconductor device having a front side and a back side opposite of the front side, metal interconnects formed on the back side, and a polymer material deposited over the first semiconductor device to encapsulate the sidewalls, back side, and metal interconnects. The first semiconductor device is planarized to expose the upper surface of the metal interconnects. The assembly further includes a second semiconductor device having a top side and a bottom side opposite of the top side, a polymer material deposited over the second semiconductor device to encapsulate the sidewalls and bottom side. The second semiconductor device is stacked over the first device and hybrid bonded together such that each metal interconnect on the first semiconductor device back side aligns with and electrically couples to a corresponding metal interconnect on the second semiconductor device bottom side.

公开(公告)号：US11410973B2

公开(公告)日：2022-08-09

申请号：US16939756

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20210272872A1

公开(公告)日：2021-09-02

申请号：US16807075

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Xiaopeng Qu ,  Hyunsuk Chun ,  Eiichi Nakano ,  Amy R. Griffin

IPC: H01L23/373 ,  H01L23/433

Abstract: Semiconductor devices including materials for thermal management, and associated systems and methods, are described herein. In some embodiments, a semiconductor package includes a first semiconductor die coupled to a second semiconductor die by a plurality of interconnect structures. A thermal material can be positioned between the first and second semiconductor dies. The thermal material can include an array of heat transfer elements embedded in a supporting matrix material. The array of heat transfer elements can include at least one vacant region aligned with at least one of the interconnect structures.

公开(公告)号：US11069612B2

公开(公告)日：2021-07-20

申请号：US16702811

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H05K1/11 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L27/146

Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.

公开(公告)号：US10943860B2

公开(公告)日：2021-03-09

申请号：US16351816

申请日：2019-03-13

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Eiichi Nakano

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01R12/77 ,  H01L41/047 ,  H01L23/538 ,  H01L23/31 ,  H01L21/683 ,  H01R12/62 ,  H01R12/71 ,  H01R12/70

Abstract: A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate.

公开(公告)号：US20210057342A1

公开(公告)日：2021-02-25

申请号：US17076602

申请日：2020-10-21

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L23/538 ,  H01L23/532 ,  H01L25/11

Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 μm). Adjacent passivation material may also be thin (e.g., less than about 0.2 μm). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.

公开(公告)号：US10580720B1

公开(公告)日：2020-03-03

申请号：US16166428

申请日：2018-10-22

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Owen R. Fay ,  Eiichi Nakano

IPC: H01L23/48 ,  H01L21/66 ,  H01L23/14 ,  H01L23/00 ,  H01L23/525 ,  H01L21/48 ,  H01L23/532

Abstract: A silicon interposer that includes an array, or pattern, of conductive paths positioned within a silicon substrate with a plurality of pins on the exterior of the substrate. Each of the pins is connected to a portion of the array of conductive paths. The array of conductive paths is configurable to provide a first electrical flow path through the substrate via a portion of the array of conductive paths or a second electrical flow path through the substrate. The electrical flow path through the substrate may be customizable for testing various die or chip layout designs. The electrical flow path through the substrate may be customizable by laser ablation of portions of the conductive paths, breaking of fuses along the conductive paths, and/or the actuation of logic gates connected to the conductive paths.

公开(公告)号：US10418255B2

公开(公告)日：2019-09-17

申请号：US15828819

申请日：2017-12-01

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L21/66 ,  H01L21/447 ,  H01L21/687

Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.