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公开(公告)号：US12222803B2
公开(公告)日：2025-02-11
申请号：US18216254
申请日：2023-06-29
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , John D. Porter
IPC: G06F11/10
Abstract: An on-die controller can provide an error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller eliminates a need to transfer error correction code (ECC) data to an external controller that may have provided the error correction capability in lieu of the on-die controller, which can provide more channel bandwidth for other types of non-user data for further strengthening data reliability, security, integrity of the memory system.
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公开(公告)号：US20250021262A1
公开(公告)日：2025-01-16
申请号：US18904757
申请日：2024-10-02
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Daniele Balluchi
IPC: G06F3/06
Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.
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公开(公告)号：US20240403177A1
公开(公告)日：2024-12-05
申请号：US18678557
申请日：2024-05-30
Applicant: Micron Technology, Inc.
Inventor： Su Wei Lim , Senthil Murugan Thangaraj , Marco Sforzin , Daniele Balluchi , Massimiliano Patriarca , Giorgio Servalli , Angelo Visconti , Antonino Capri’ , Garth N. Grubb , Amitava Majumdar , Miguel Mares
Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.
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公开(公告)号：US20240356567A1
公开(公告)日：2024-10-24
申请号：US18631870
申请日：2024-04-10
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Christophe Vincent Antoine Laurent
CPC classification number: H03M13/152 , G06F11/1044 , G06F11/1048 , H03M13/1575
Abstract: Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.
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公开(公告)号：US20240356566A1
公开(公告)日：2024-10-24
申请号：US18631840
申请日：2024-04-10
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Christophe Vincent Antoine Laurent
CPC classification number: H03M13/152 , H03M13/1108 , H03M13/1575
Abstract: Systems and methods for fast multi-length payload error correcting includes at least a decoder circuit. The decoder circuit receives a first input and receives a second input. The decoder circuit generates, based on the first input, a first decoded payload. The first decoded payload includes at least a first data or a first length and a first flip bit. The decoder circuit generates, based on the second input, a second decoded payload. The second decoded payload includes at least a second data of a second length and a second flip bit, the second length being different from the first length.
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Patent Agency Ranking
公开(公告)号：US20240355395A1
公开(公告)日：2024-10-24
申请号：US18759032
申请日：2024-06-28
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Luca Barletta , Marco Pietro Ferrari , Antonino Favano
CPC classification number: G11C16/102 , G11C16/12 , G11C16/3404
Abstract: The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a threshold voltage value of each cell of the codeword, sort the threshold voltage values, determine a second derivative value of a cell metric for a number of the cells of the codeword based on the threshold voltage value of that respective cell, the threshold voltage value immediately preceding the threshold voltage value of that respective cell in the sorted values, and a value proportional to a total quantity of the cells of the codeword, determine the cell metric for which the determined second derivative value has a greatest value, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.
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公开(公告)号：US12112057B2
公开(公告)日：2024-10-08
申请号：US17861233
申请日：2022-07-10
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Daniele Balluchi
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673
Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.
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公开(公告)号：US12088322B2
公开(公告)日：2024-09-10
申请号：US17894777
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato
CPC classification number: H03M13/19 , H03M13/159 , H03M13/617
Abstract: There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.
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公开(公告)号：US20240111629A1
公开(公告)日：2024-04-04
申请号：US17959412
申请日：2022-10-04
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Joseph M. McCrate
IPC: G06F11/10
CPC classification number: G06F11/1096
Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
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公开(公告)号：US20240071448A1
公开(公告)日：2024-02-29
申请号：US17895053
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato
CPC classification number: G11C7/24 , G11C7/1012 , G11C7/109
Abstract: Systems, apparatus, and methods related to configurable data protection circuitry. A memory includes a plurality of memory devices and a memory controller that can be coupled to the memory via a plurality of channels. The channels comprise respective subsets of the plurality of memory devices. The memory controller comprises data protection circuitry to accommodate a first codeword configuration of a number of codewords responsive to the plurality of memory devices having a first operating mode corresponding to a first input/output (I/O) width and accommodate a second codeword configuration of the number of codewords responsive to the plurality of memory devices having a second operating mode corresponding to a second I/O width, as well as switch between the first operating mode of the plurality of memory devices and the second operating mode of the plurality of memory devices.
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