公开(公告)号：US10074407B2

公开(公告)日：2018-09-11

申请号：US14724366

申请日：2015-05-28

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Richard C. Murphy

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4093

CPC classification number: G11C7/08 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4093

Abstract: Apparatuses and methods related to performing logical operations using sensing circuitry are disclosed. One example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a compute component. The sensing circuitry is configured to invert a data value in the compute component.

公开(公告)号：US10056122B2

公开(公告)日：2018-08-21

申请号：US15692376

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G11C15/04 ,  G11C7/12 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4091

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

公开(公告)号：US10025593B2

公开(公告)日：2018-07-17

申请号：US14980024

申请日：2015-12-28

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

Abstract: The present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US20180190334A1

公开(公告)日：2018-07-05

申请号：US15899187

申请日：2018-02-19

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/22 ,  G06F3/06 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/068 ,  G06F7/523 ,  G06F12/00 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4091 ,  H03K19/0013 ,  H03K19/1776

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

公开(公告)号：US09934856B2

公开(公告)日：2018-04-03

申请号：US14667868

申请日：2015-03-25

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C15/04 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4091

CPC classification number: G11C15/043 ,  G11C7/1006 ,  G11C11/4091

Abstract: Apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.

公开(公告)号：US09899068B2

公开(公告)日：2018-02-20

申请号：US15439681

申请日：2017-02-22

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C16/04 ,  H03K19/00 ,  G11C7/22 ,  G11C7/10 ,  G11C7/06 ,  G06F3/06

CPC classification number: G11C7/22 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/068 ,  G06F7/523 ,  G06F12/00 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4091 ,  H03K19/0013 ,  H03K19/1776

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

公开(公告)号：US20170301377A1

公开(公告)日：2017-10-19

申请号：US15642723

申请日：2017-07-06

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Richard C. Murphy

IPC: G11C7/06 ,  G11C11/4078 ,  G11C7/22 ,  G06F11/10 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/24

CPC classification number: G11C7/06 ,  G06F11/10 ,  G06F11/1048 ,  G11C7/10 ,  G11C7/22 ,  G11C7/24 ,  G11C11/4078 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.

公开(公告)号：US09767886B2

公开(公告)日：2017-09-19

申请号：US15093273

申请日：2016-04-07

Applicant: Micron Technology, Inc.

Inventor： Joo S Choi ,  Troy A. Manning ,  Brent Keeth

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

公开(公告)号：US09696910B2

公开(公告)日：2017-07-04

申请号：US14867139

申请日：2015-09-28

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley ,  Jeffrey L. Meader ,  Steve G. Bard ,  Dean C. Eyres

IPC: G06F3/06 ,  H03M7/30

CPC classification number: G06F3/0608 ,  G06F3/0661 ,  G06F3/0673 ,  H03M7/30 ,  H03M7/60 ,  H03M7/6082

Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.

公开(公告)号：US20170053693A1

公开(公告)日：2017-02-23

申请号：US15346526

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Troy A. Manning ,  Richard C. Murphy

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4096

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Abstract translation: 本公开的一个示例包括使用存储在耦合到存储器阵列的感测线的多个存储器单元的第一部分中的第一值的逻辑表示和存储的第二值的逻辑表示来在存储器中执行比较操作 在耦合到存储器阵列的感测线的存储器单元的数量的第二部分中。 比较操作将第一值与第二值进行比较，并且该方法可以包括将比较操作的结果的逻辑表示存储在耦合到存储器阵列的感测线的存储器单元的数量的第三部分中。