公开(公告)号：US20220005819A1

公开(公告)日：2022-01-06

申请号：US16921641

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Shyam Surthi ,  Matthew Thorum

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The channel-material-string constructions individually comprise a channel-material string that extends through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. The undoped silicon dioxide-comprising strings are etched through the void space in the second tiers left by the etching of the doped silicon dioxide to divide individual of the undoped silicon dioxide-comprising strings into vertically-spaced segments of the undoped silicon dioxide. Structure independent of method is disclosed.

公开(公告)号：US20210167089A1

公开(公告)日：2021-06-03

申请号：US17177357

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Richard J. Hill ,  John D. Hopkins ,  Collin Howder

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

公开(公告)号：US20210151454A1

公开(公告)日：2021-05-20

申请号：US17160956

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US20200266204A1

公开(公告)日：2020-08-20

申请号：US16869194

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H01L27/11556 ,  G11C5/06 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier. The conductive structure extends through the first insulator tier and directly electrically couples the channel material to the conductive tier. Structure embodiments are disclosed.

公开(公告)号：US10573661B2

公开(公告)日：2020-02-25

申请号：US16363296

申请日：2019-03-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11519 ,  H01L27/11565

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US10236301B1

公开(公告)日：2019-03-19

申请号：US15890503

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Ryan M. Meyer ,  Chet E. Carter

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3205

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming conductively-doped semiconductor material directly above and electrically coupled to metal material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed directly above the conductively-doped semiconductor material. Horizontally-elongated trenches are formed through the stack to the conductively-doped semiconductor material. The conductively-doped semiconductor material is oxidized through the trenches to form an oxide therefrom that is directly above the metal material. Transistor channel material is provided to extend elevationally along the alternating tiers. The wordline tiers are provided to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is between the transistor channel material and the control-gate regions. Insulative charge-passage material is between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

公开(公告)号：US12230325B2

公开(公告)日：2025-02-18

申请号：US17409300

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Collin Howder ,  Jordan D. Greenlee

IPC: H01L21/768 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240021521A1

公开(公告)日：2024-01-18

申请号：US17812616

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Martin Jared Barclay ,  Harsh Narendrakumar Jain ,  Yiping Wang

IPC: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L23/535 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11573

Abstract: Methods, systems, and devices for staircase structures for accessing three-dimensional (3D) memory arrays are described. A memory system may include an access region (e.g., a staircase region) that includes circuitry for accessing memory cells at respective levels of memory cells. The access region may include a channel through which a conductive pillar may couple a word line at a level of memory cells with decoder circuitry. During manufacture of the memory system, a channel material may be formed in the channel and etched to form a corner portion in the channel. During a partitioning of the channel, a nitride material over the corner portion may be etched and some of the corner portion may remain in the channel, which may prevent formation of a trench that may cause the conductive pillar to be uncoupled from the word line.

公开(公告)号：US20230386575A1

公开(公告)日：2023-11-30

申请号：US17752207

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Haoyu Li ,  John D. Hopkins ,  Collin Howder ,  Adam W. Saxler

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. The intermediate material is of different composition from those of the upper conductively-doped semiconductive material and the lower conductively-doped semiconductive material and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. Other embodiments, including method, re disclosed.

公开(公告)号：US20230320092A1

公开(公告)日：2023-10-05

申请号：US17713955

申请日：2022-04-05

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions individually comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. Conductive material in the lowest conductive tier directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conductive material is laterally-aside and laterally-inward of a laterally-inner sidewall of the charge-blocking-material string. Methods are disclosed.