公开(公告)号：US20170261956A1

公开(公告)日：2017-09-14

申请号：US15605542

申请日：2017-05-25

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning

IPC: G05B19/045 ,  G06F21/56 ,  G06N5/04 ,  H03K19/177 ,  G06F15/82 ,  G06F9/44

CPC classification number: G05B19/045 ,  G06F9/4498 ,  G06F15/82 ,  G06F21/567 ,  G06F2207/025 ,  G06N5/047 ,  H03K19/17724 ,  H03K19/17748

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

公开(公告)号：US09535861B2

公开(公告)日：2017-01-03

申请号：US15045550

申请日：2016-02-17

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Irene Junjuan Xu ,  Paul Glendenning

IPC: G06F7/38 ,  G06F13/16 ,  H04L12/883 ,  G06F13/42 ,  G06F13/40 ,  G06F13/12

CPC classification number: G06F13/1673 ,  G06F9/4498 ,  G06F13/124 ,  G06F13/4022 ,  G06F13/4282 ,  G06F17/30516 ,  G06K9/00496 ,  G06K9/00973 ,  G06K9/00979 ,  H04L49/9021

Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.

Abstract translation: 设备包括路由缓冲区。 路由缓冲器包括被配置为接收与数据流的至少一部分的分析有关的信号的第一端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第一路由线的第二端口。 路由缓冲器还包括被配置为在第一时间将信号选择性地提供给状态机的块的第二路由选择线的第三端口。

公开(公告)号：US20160217365A1

公开(公告)日：2016-07-28

申请号：US15090305

申请日：2016-04-04

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06N3/04

CPC classification number: G06N3/04 ,  G05B19/045 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/02

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

Abstract translation: 具有程序缓冲器的状态机引擎。 程序缓冲器被配置为经由总线接口接收用于配置状态机格子的配置数据。 状态机引擎还包括配置为经由总线接口向外部设备提供修复地图数据的修复地图缓冲器。 状态机格子包括多个可编程元件。 每个可编程元件包括配置成分析数据并输出分析结果的多个存储器单元。

公开(公告)号：US09280329B2

公开(公告)日：2016-03-08

申请号：US14329586

申请日：2014-07-11

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F9/45 ,  G06F9/44 ,  G06F9/00 ,  G06K9/00

CPC classification number: G06F9/444 ,  G06F8/45 ,  G06F9/4498 ,  G06K9/00986

Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate.

Abstract translation: 一种包括包括多个存储单元的数据分析单元的设备。 存储器单元分析数据流的至少一部分并输出分析结果。 该装置还包括检测单元。 检测单元包括与门。 与门接收分析结果作为第一输入。 检测单元还包括D触发器，其包括耦合到与门的第二输入的输出。

公开(公告)号：US09118327B2

公开(公告)日：2015-08-25

申请号：US14087973

申请日：2013-11-22

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

IPC: G05B19/045 ,  G06F7/00 ,  G06F3/037 ,  H03K19/0175 ,  H03K19/20 ,  G06F17/50

CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

公开(公告)号：US20240211761A1

公开(公告)日：2024-06-27

申请号：US18598738

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes

IPC: G06N3/08 ,  G06F1/3206 ,  G06F1/3287 ,  G06V10/94

CPC classification number: G06N3/08 ,  G06F1/3206 ,  G06F1/3287 ,  G06V10/94 ,  G06V10/955 ,  Y02D10/00

Abstract: A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows includes a plurality of programmable elements. Furthermore, each of the programmable elements are configured to analyze at least a portion of a data stream and to selectively output a result of the analysis. Each of the plurality of blocks also has corresponding block activation logic configured to dynamically power-up

公开(公告)号：US11741014B2

公开(公告)日：2023-08-29

申请号：US17979472

申请日：2022-11-02

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit Singh Bains

IPC: G06F12/08 ,  G06F12/0875 ,  G06F9/448 ,  G06N3/02 ,  G06F3/06

CPC classification number: G06F12/0875 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0683 ,  G06F9/4498 ,  G06N3/02 ,  G06F2212/60

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

公开(公告)号：US20230196065A1

公开(公告)日：2023-06-22

申请号：US18110162

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06N3/04 ,  G06F9/448 ,  G06F15/78 ,  G05B19/045 ,  G06N3/02

CPC classification number: G06N3/04 ,  G06F9/4498 ,  G06F15/7867 ,  G05B19/045 ,  G06N3/02

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

公开(公告)号：US20210142082A1

公开(公告)日：2021-05-13

申请号：US17154671

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Steven P. King

IPC: G06K9/00 ,  G06F16/9032

Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.

公开(公告)号：US10977309B2

公开(公告)日：2021-04-13

申请号：US15286202

申请日：2016-10-05

Applicant: Micron Technology, Inc.

Inventor： Paul Glendenning ,  Michael C. Leventhal ,  Paul Dlugosch ,  Harold B Noyes

IPC: G06F16/901 ,  G06F16/904 ,  G06N3/00 ,  G06F8/41 ,  G06F8/34 ,  G06F30/20

Abstract: The Automata Processor Workbench (AP Workbench) is an application for creating and editing designs of AP networks (e.g., one or more portions of the state machine engine, one or more portions of the FSM lattice, or the like) based on, for example, an Automata Network Markup Language (ANML). For instance, the application may include a tangible, non-transitory computer-readable medium configured to store instructions executable by a processor of an electronic device, wherein the instructions include instructions to represent an automata network as a graph.