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公开(公告)号：US08524570B2
公开(公告)日：2013-09-03
申请号：US12890995
申请日：2010-09-27
IPC分类号： H01L21/76
CPC分类号： H01L29/78 , H01L21/76224 , H01L21/76232 , H01L21/823456 , H01L21/823475 , H01L21/823481 , H01L27/088
摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.
摘要翻译： 一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成 在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的触点。
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42.发明授权Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers 有权在两个氧气密封层之间具有含氧层的场效应晶体管的间隔结构公开(公告)号：US08450834B2
公开(公告)日：2013-05-28
申请号：US12706191
申请日：2010-02-16
IPC分类号： H01L21/8238
CPC分类号： H01L29/401 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.
摘要翻译： 本公开涉及场效应晶体管的间隔结构。 场效应晶体管的示例性结构包括：衬底; 栅极结构，其具有覆盖所述衬底的侧壁; 所述栅极结构的一侧上的所述衬底中的硅化物区域具有最靠近所述栅极结构的内部边缘; 与栅极结构的侧壁相邻的第一氧气密封层; 邻接所述侧壁上的所述第一氧气密封层并且还包括在所述衬底上延伸的部分的含氧层; 以及邻接所述含氧层并在所述基底上的所述含氧层的所述部分上延伸的第二氧气密封层，其中所述第二氧气密封层的外边缘从所述硅化物区域的内边缘偏移。
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公开(公告)号：US20110198675A1
公开(公告)日：2011-08-18
申请号：US12706191
申请日：2010-02-16
IPC分类号： H01L29/78 , H01L21/311
CPC分类号： H01L29/401 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： This disclosure relates to a spacer structure of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate structure that has a sidewall overlying the substrate; a silicide region in the substrate on one side of the gate structure having an inner edge closest to the gate structure; a first oxygen-sealing layer adjoining the sidewall of the gate structure; an oxygen-containing layer adjoining the first oxygen-sealing layer on the sidewall and further including a portion extending over the substrate; and a second oxygen-sealing layer adjoining the oxygen-containing layer and extending over the portion of the oxygen-containing layer over the substrate, wherein an outer edge of the second oxygen-sealing layer is offset from the inner edge of the silicide region.
摘要翻译： 本公开涉及场效应晶体管的间隔结构。 场效应晶体管的示例性结构包括：衬底; 栅极结构，其具有覆盖所述衬底的侧壁; 所述栅极结构的一侧上的所述衬底中的硅化物区域具有最靠近所述栅极结构的内部边缘; 与栅极结构的侧壁相邻的第一氧气密封层; 邻接所述侧壁上的所述第一氧气密封层并且还包括在所述衬底上延伸的部分的含氧层; 以及邻接所述含氧层并在所述基底上的所述含氧层的所述部分上延伸的第二氧气密封层，其中所述第二氧气密封层的外边缘从所述硅化物区域的内边缘偏移。
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公开(公告)号：US09093559B2
公开(公告)日：2015-07-28
申请号：US13415967
申请日：2012-03-09
申请人： Jin-Aun Ng , Po-Nien Chen , Sheng-Chen Chung , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Po-Nien Chen , Sheng-Chen Chung , Bao-Ru Young , Hak-Lay Chuang
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.
摘要翻译： 公开了一种制造具有混合HK /金属栅极堆叠制造的半导体器件的工艺。 该方法包括提供在PFET区域和NFET区域之间具有多个隔离特征的半导体衬底，以及在半导体衬底上形成栅叠层。 在PFET区域中，栅极堆叠形成为HK /金属栅极。 在NFET区域中，栅堆叠形成为多晶硅栅极。 通过利用另一个多晶硅栅极也在半导体衬底上形成高电阻。
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公开(公告)号：US20120074498A1
公开(公告)日：2012-03-29
申请号：US12890995
申请日：2010-09-27
IPC分类号： H01L21/762 , H01L27/088
CPC分类号： H01L29/78 , H01L21/76224 , H01L21/76232 , H01L21/823456 , H01L21/823475 , H01L21/823481 , H01L27/088
摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.
摘要翻译： 一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成 在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。 不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有 设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的触点。
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公开(公告)号：US08890260B2
公开(公告)日：2014-11-18
申请号：US12554604
申请日：2009-09-04
申请人： Harry Hak-Lay Chuang , Kong-Beng Thei , Sheng-Chen Chung , Chiung-Han Yeh , Lee-Wee Teo , Yu-Ying Hsu , Bao-Ru Young
发明人： Harry Hak-Lay Chuang , Kong-Beng Thei , Sheng-Chen Chung , Chiung-Han Yeh , Lee-Wee Teo , Yu-Ying Hsu , Bao-Ru Young
IPC分类号： H01L29/78 , H01L27/06 , H01L27/092 , H01L29/66 , H01L21/8238 , H01L49/02
CPC分类号： H01L29/66545 , H01L21/823842 , H01L27/0629 , H01L27/0802 , H01L27/0922 , H01L28/20 , H01L29/6659 , H01L29/7833 , H01L2223/6672
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
摘要翻译： 本发明提供集成电路。 集成电路包括半导体衬底; 以及设置在半导体衬底上的无源多晶硅器件。 无源多晶硅器件还包括多晶硅特征; 以及嵌入在多晶硅特征中的多个电极。
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公开(公告)号：US20110042750A1
公开(公告)日：2011-02-24
申请号：US12897559
申请日：2010-10-04
申请人： Harry-Hak-Lay Chuang , Bao-Ru Young , Kuei Shun Chen , Cheng Cheng Kuo , George Liu , Tsung-Chieh Tsai , Yuhi-Jier Mii
发明人： Harry-Hak-Lay Chuang , Bao-Ru Young , Kuei Shun Chen , Cheng Cheng Kuo , George Liu , Tsung-Chieh Tsai , Yuhi-Jier Mii
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/28123 , H01L21/823437 , H01L27/0207 , H01L29/0653 , H01L29/0696 , H01L29/42376 , H01L29/4238 , H01L29/4966 , H01L29/66545 , H01L29/66606 , H01L29/7831
摘要： Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.
摘要翻译： 公开了形成半导体结构和半导体结构的方法。 在一个实施例中，一种方法包括在衬底上形成栅极电介质层，在栅极电介质层上形成栅极电极层，并蚀刻栅极电极层和栅极电介质层以形成水平栅极结构和垂直栅极结构， 其中所述水平栅极结构和所述垂直栅极结构通过互连部分连接。 该方法还包括形成覆盖水平栅极结构和垂直栅极结构的光致抗蚀剂，其中光致抗蚀剂具有暴露水平栅极结构和垂直栅极结构之间的互连部分的间隙，然后蚀刻互连部分。
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公开(公告)号：US20130056837A1
公开(公告)日：2013-03-07
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译： 制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。 在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。 薄介电膜包括从金属栅极与金属组合的氮氧化合物。 该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。
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公开(公告)号：US08343867B2
公开(公告)日：2013-01-01
申请号：US13234674
申请日：2011-09-16
申请人： Jin-Aun Ng , Yu-Ying Hsu , Chi-Ju Lee , Sin-Hua Wu , Bao-Ru Young , Harry-Hak-Lay Chuang
发明人： Jin-Aun Ng , Yu-Ying Hsu , Chi-Ju Lee , Sin-Hua Wu , Bao-Ru Young , Harry-Hak-Lay Chuang
IPC分类号： H01L21/4763
CPC分类号： H01L21/823425 , H01L21/823468 , H01L21/823475
摘要： The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.
摘要翻译： 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层（或硬掩模）在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀（或修整）工艺的工艺均匀性（或控制）确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要，例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物，并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好，接触良好的硅化物提高了接触的收率，并使接触电阻达到可接受和可操作的范围。
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公开(公告)号：US20130234254A1
公开(公告)日：2013-09-12
申请号：US13415967
申请日：2012-03-09
申请人： Jin-Aun Ng , Po-Nien Chen , Sheng-Chen Chung , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Po-Nien Chen , Sheng-Chen Chung , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate.
摘要翻译： 公开了一种制造具有混合HK /金属栅极堆叠制造的半导体器件的工艺。 该方法包括提供在PFET区域和NFET区域之间具有多个隔离特征的半导体衬底，以及在半导体衬底上形成栅叠层。 在PFET区域中，栅极堆叠形成为HK /金属栅极。 在NFET区域中，栅堆叠形成为多晶硅栅极。 通过利用另一个多晶硅栅极也在半导体衬底上形成高电阻。
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