公开(公告)号：US09448867B2

公开(公告)日：2016-09-20

申请号：US13997046

申请日：2011-12-31

Applicant: Shamanna M. Datta ,  Rajesh S. Parathasarathy ,  Mahesh S. Natu ,  Frank Binns ,  Mohan J. Kumar

Inventor： Shamanna M. Datta ,  Rajesh S. Parathasarathy ,  Mahesh S. Natu ,  Frank Binns ,  Mohan J. Kumar

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/14 ,  G06F21/52

CPC classification number: G06F11/0754 ,  G06F12/1441 ,  G06F21/52

Abstract: A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.

Abstract translation: 描述了一种方法，其包括通过将系统管理程序代码的存储器访问指令的目标存储器地址再次比较来检测系统管理模式程序代码的存储器访问尝试到达存储器的受保护区域之外的程序代码， 定义保护区域的范围。 该方法还包括响应于检测而提高误差信号。

公开(公告)号：US09405646B2

公开(公告)日：2016-08-02

申请号：US13992506

申请日：2011-09-29

Applicant: Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

Inventor： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/36

CPC classification number: G06F11/263 ,  G06F11/3664 ,  G06F11/3688

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Abstract translation: 公开了一种向存储器注入错误的装置和方法。 在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。 如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

公开(公告)号：US20150378808A1

公开(公告)日：2015-12-31

申请号：US14319387

申请日：2014-06-30

Applicant: Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Camille C. Raad

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Camille C. Raad

IPC: G06F11/07

CPC classification number: G06F11/073 ,  G06F11/0769 ,  G06F11/0787 ,  G09C1/00 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0409

Abstract: Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM.

Abstract translation: 示例可以包括用于与用于非易失性双列直插式存储器模块（NVDIMM）的控制器通信的计算平台的基本输入/输出系统（BIOS）。 BIOS和控制器之间的通信可以包括控制器在NVDIMM下扫描和识别非易失性存储器中的错误位置的请求。 非易失性存储器可能能够为NVDIMM提供持久存储器。

公开(公告)号：US20150161037A1

公开(公告)日：2015-06-11

申请号：US14100721

申请日：2013-12-09

Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Eswaramoorthi Nallusamy

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Eswaramoorthi Nallusamy

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1032 ,  G06F2212/7203

Abstract: Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in a volatile memory, determine whether the first data element is to be stored in a nonvolatile memory, and in response to a determination that the first data element is to be stored in a nonvolatile memory, to forward the first transaction to the memory controller coupled to the nonvolatile memory. Other examples are also disclosed and claimed.

Abstract translation: 描述了管理存储器操作的装置，系统和方法。 在一个示例中，控制器包括接收第一事务以操作易失性存储器中的第一数据元素的逻辑，确定第一数据元素是否要存储在非易失性存储器中，并且响应于确定第一数据 元件将被存储在非易失性存储器中，以将第一事务转发到耦合到非易失性存储器的存储器控​​制器。 还公开并要求保护其他实例。

公开(公告)号：US20140281092A1

公开(公告)日：2014-09-18

申请号：US13799327

申请日：2013-03-13

Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

IPC: G06F13/24

CPC classification number: G06F9/4812 ,  G06F11/0772

Abstract: Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.

Abstract translation: 用于系统管理中断（“SMI”）处理的技术包括配置为响应于检测到SMI而进入系统管理模式（“SMM”）的多个处理器核心。 进入SMM并获取主线程锁的第一个处理器核心设置正在进行的标志，并执行主SMI处理程序，而不必等待其他处理器内核进入SMM。 其他处理器核心执行从属SMI处理程序。 主SMI处理程序可以指示下级SMI处理程序来处理核心特定的SMI。 响应于检测到由获取主线程锁的处理器核心清除的SMI，多核处理器可以设置SMI服务挂起标志。 进入SMM的处理器核心在确定进行中标志未被设置并且未设置服务暂挂标志时，可以立即恢复正常执行，以检测和减轻假SMI。 描述和要求保护其他实施例。

公开(公告)号：US20130332781A1

公开(公告)日：2013-12-12

申请号：US13997870

申请日：2012-06-06

Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0712 ,  G06F11/0745 ,  G06F11/0793

Abstract: Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

Abstract translation: 本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器 输入/输出错误容纳事件。 在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

公开(公告)号：US08578138B2

公开(公告)日：2013-11-05

申请号：US12550737

申请日：2009-08-31

Applicant: Mahesh S. Natu ,  Thanunathan Rangarajan ,  Gautam B. Doshi ,  Shammanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

Inventor： Mahesh S. Natu ,  Thanunathan Rangarajan ,  Gautam B. Doshi ,  Shammanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

IPC: G06F9/48

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。

公开(公告)号：US20130290759A1

公开(公告)日：2013-10-31

申请号：US13976901

申请日：2011-12-13

Applicant: Mohan J. Kumar ,  Murugasamy K. Nachimuthu

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/4418 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.

Abstract translation: 在计算机系统中使用非易失性随机存取存储器（NVRAM）来增强对睡眠状态的支持。 计算机系统包括处理器，可字节可重写和字节可擦除的非易失性随机存取存储器（NVRAM）和电源管理（PM）模块。 动态随机存取存储器（DRAM）提供系统地址空间的一部分。 PM模块拦截由操作系统启动进入休眠状态的请求，将数据从DRAM复制到NVRAM，将系统地址空间的一部分映射到NVRAM，并将DRAM转换为 睡眠状态。 在发生唤醒事件时，PM模块向操作系统返回控制，使得计算机系统恢复工作状态操作，而操作系统不知道系统地址空间的一部分已经映射到NVRAM。

公开(公告)号：US20130275682A1

公开(公告)日：2013-10-17

申请号：US13994729

申请日：2011-09-30

Applicant: Raj K. Ramanujan ,  Dimitrios Ziakas ,  David J. Zimmerman ,  Mohan J. Kumar ,  Muthukumar P. Swaminathan ,  Bassam N Coury

Inventor： Raj K. Ramanujan ,  Dimitrios Ziakas ,  David J. Zimmerman ,  Mohan J. Kumar ,  Muthukumar P. Swaminathan ,  Bassam N Coury

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0238 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0848 ,  G06F12/0866 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2024 ,  G06F2212/304

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

Abstract translation: 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。 更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。 这些更高性能的存储器件被称为“接近存储器”。

公开(公告)号：US20120265998A1

公开(公告)日：2012-10-18

申请号：US13532334

申请日：2012-06-25

Applicant: Mohan J. Kumar ,  Shay Gueron

Inventor： Mohan J. Kumar ,  Shay Gueron

IPC: G06F21/00

CPC classification number: G06F21/57 ,  G06F21/575 ,  G06F2221/2129

Abstract: When a processing system boots, it may retrieve an encrypted version of a cryptographic key from nonvolatile memory to a processing unit, which may decrypt the cryptographic key. The processing system may also retrieve a predetermined authentication code for software of the processing system, and the processing system may use the cryptographic key to compute a current authentication code for the software. The processing system may then determine whether the software should be trusted, by comparing the predetermined authentication code with the current authentication code. In various embodiments, the processing unit may use a key stored in nonvolatile storage of the processing unit to decrypt the encrypted version of the cryptographic key, a hashed message authentication code (HMAC) may be used as the authentication code, and/or the software to be authenticated may be boot firmware, a virtual machine monitor (VMM), or other software. Other embodiments are described and claimed.

Abstract translation: 当处理系统引导时，它可以从非易失性存储器检索加密密钥的加密版本到处理单元，该处理单元可以解密密码密钥。 处理系统还可以检索用于处理系统的软件的预定认证码，并且处理系统可以使用密码密钥来计算软件的当前认证码。 然后，处理系统可以通过将预定认证码与当前认证码进行比较来确定软件是否应该被信任。 在各种实施例中，处理单元可以使用存储在处理单元的非易失性存储器中的密钥对加密密钥的加密版本进行解密，散列消息认证码（HMAC）可以用作认证码，和/或软件 被认证可以是启动固件，虚拟机监视器（VMM）或其他软件。 描述和要求保护其他实施例。