公开(公告)号：US07579685B2

公开(公告)日：2009-08-25

申请号：US11339500

申请日：2006-01-26

申请人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

发明人： Moon-chul Lee ,  Woon-bae Kim ,  Kae-dong Back ,  Qian Wang ,  Jun-sik Hwang ,  Kyu-dong Jung

IPC分类号： H01L23/12 ,  H01L23/043

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/10 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.

摘要翻译： 提供了一种用于晶片级封装的晶片级封装盖及其方法。 覆盖其上具有器件的器件晶片的晶片级封装盖包括盖晶片，其在底表面上具有提供用于接收器件的空间并与器件晶片整体结合的空腔，形成在底部的多个金属线 盖片晶片的表面对应于形成在器件晶片上以电连接到器件的多个器件焊盘，多个缓冲部分连接到多个金属线并且包括具有多个沟槽的缓冲晶片和 填充在所述多个槽中的金属，多个连接杆，电连接到所述多个缓冲部分，并且从所述缓冲部分的顶部穿透所述盖片;以及形成在所述盖片的顶表面上的多个帽垫 并且电连接到多个连接杆。

公开(公告)号：US07432781B2

公开(公告)日：2008-10-07

申请号：US11392624

申请日：2006-03-30

申请人： Sang-chul Sul ,  Duck-hwan Kim ,  Chul-soo Kim ,  In-sang Song ,  Moon-chul Lee ,  Kyu-dong Jung ,  Jea-shik Shin

发明人： Sang-chul Sul ,  Duck-hwan Kim ,  Chul-soo Kim ,  In-sang Song ,  Moon-chul Lee ,  Kyu-dong Jung ,  Jea-shik Shin

IPC分类号： H03H7/46

CPC分类号： H03H3/02 ,  H03H9/0571 ,  H03H9/706

摘要： A monolithic duplexer and a fabrication method thereof. The monolithic duplexer includes a device wafer, a plurality of elements distanced from each other on a top portion of a device wafer, first sealing parts formed on the top portion of the device wafer, and a plurality of first ground planes formed between the plurality of elements. A cap wafer is also provided having an etched area for packaging the device wafer, a plurality of protrusion parts, a plurality of ground posts, and cavities. Second sealing parts are formed on a bottom portion of the protrusion parts, and a plurality of second ground planes cover the plurality of ground posts. Via holes vertically penetrate the cap wafer to connect to the plurality of the second ground planes, and ground terminals are formed on top portions of the via holes. The first sealing parts and the first ground planes are attached to the second sealing parts and the second ground planes, respectively.

摘要翻译： 一种单片双工器及其制造方法。 单片双工器包括器件晶片，在器件晶片的顶部彼此远离的多个元件，形成在器件晶片的顶部上的第一密封部分和形成在器件晶片的顶部之间的多个第一接地平面 元素。 还提供了盖晶片，其具有用于封装器件晶片，多个突出部分，多个接地柱和空腔的蚀刻区域。 第二密封部分形成在突出部分的底部上，并且多个第二接地平面覆盖多个接地柱。 通孔垂直穿过盖晶片以连接到多个第二接地平面，并且接地端子形成在通孔的顶部上。 第一密封部分和第一接地平面分别附接到第二密封部分和第二接地平面。

公开(公告)号：US07408257B2

公开(公告)日：2008-08-05

申请号：US11390220

申请日：2006-03-28

申请人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

发明人： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

IPC分类号： H01L23/04

CPC分类号： H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

摘要翻译： 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

公开(公告)号：US07335974B2

公开(公告)日：2008-02-26

申请号：US11391211

申请日：2006-03-29

申请人： Jun-sik Hwang ,  Woon-bae Kim ,  Chang-youl Moon ,  Moon-chul Lee ,  Kyu-dong Jung

发明人： Jun-sik Hwang ,  Woon-bae Kim ,  Chang-youl Moon ,  Moon-chul Lee ,  Kyu-dong Jung

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： B81C1/0023 ,  B81B7/007 ,  B81C2203/0118 ,  H01L23/04 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48463 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/16235 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.

摘要翻译： 提供了一种多层封装芯片及其制造方法。 该方法包括在第一晶片上形成至少一个第二电路元件; 形成具有空腔的第二晶片和与所述腔相对形成的一个第三电路元件; 在第二晶片上形成焊料; 以及将所述第二晶片与所述第一晶片组合以使得所述第二电路元件和所述空腔对应。 芯片包括倒装芯片封装芯片，其中使用第一晶片封装第一电路元件; 形成在第一晶片上的第二电路元件; 第二晶片，其具有空腔并与所述第一晶片组合，使得所述空腔和所述第二电路元件对应; 形成在第二晶片上的第三电路元件; 以及形成在所述第二晶片上的焊料，所述焊料将所述第二晶片电耦合到封装衬底。

公开(公告)号：US06975010B2

公开(公告)日：2005-12-13

申请号：US10320679

申请日：2002-12-17

申请人： Eun-sung Lee ,  Moon-chul Lee ,  Hyun-ok Kim

发明人： Eun-sung Lee ,  Moon-chul Lee ,  Hyun-ok Kim

IPC分类号： B81C1/00 ,  B81B3/00 ,  H01L29/82

CPC分类号： B81B3/0078 ,  B81B2203/0307 ,  B81C2201/0109

摘要： A fabrication method for a MEMS structure, the MEMS structure including a fixing portion fixed to the substrate and a floating portion floating above the substrate. A sacrificial layer deposited on the substrate is patterned to have a groove forming a space surrounding the area corresponding to the area in which the fixing portion is to be formed. If the MEMS structure is deposited on the sacrificial layer, a sidewall is formed inside the space and the fixing portion and the floating portion are formed on the sacrificial layer. If the sacrificial layer is removed using an etchant, the sacrificial layer at the bottom of the fixing portion is protected from the etchant by the sidewall and accordingly, the sacrificial layer except the area surrounded by the sidewall is removed. Therefore, only the sacrificial layer under the floating portion is removed. Because the connecting portion is fabricated to have the same thickness as the fixing portion and the floating portion, a strong/durable MEMS structure is provided. Additionally, the boundary between the fixing portion and the floating portion can be precisely determined, and adjustment of the length of the floating portion can be precisely controlled.

摘要翻译： 一种用于MEMS结构的制造方法，所述MEMS结构包括固定到所述基板的固定部分和浮置在所述基板上方的浮动部分。 沉积在基板上的牺牲层被图案化以具有形成围绕与要形成固定部分的区域相对应的区域的空间的凹槽。 如果MEMS结构沉积在牺牲层上，则在空间内形成侧壁，并且在牺牲层上形成固定部分和浮动部分。 如果使用蚀刻剂去除牺牲层，则固定部分底部的牺牲层被侧壁保护而不受蚀刻剂的影响，因此除去由侧壁包围的区域之外的牺牲层。 因此，只有在浮动部分下面的牺牲层被去除。 由于连接部分被制造成具有与固定部分和浮动部分相同的厚度，所以提供了强/耐久的MEMS结构。 此外，可以精确地确定固定部分和浮动部分之间的边界，并且可以精确地控制浮动部分的长度的调节。

公开(公告)号：US20050266472A1

公开(公告)日：2005-12-01

申请号：US11139571

申请日：2005-05-31

申请人： Tae-sik Park ,  Sung-hee Lee ,  Jung-ho Kang ,  Young-il Kim ,  Moon-chul Lee ,  Jong-hwa Won

发明人： Tae-sik Park ,  Sung-hee Lee ,  Jung-ho Kang ,  Young-il Kim ,  Moon-chul Lee ,  Jong-hwa Won

IPC分类号： G01N22/00 ,  C12M1/00 ,  C12N15/09 ,  C12Q1/68 ,  G01N27/00 ,  G01N27/02 ,  G01N27/22 ,  G01N33/487 ,  G01N37/00 ,  C12M1/34 ,  H01F21/02

CPC分类号： G01N27/3276

摘要： An apparatus and method for detecting bio molecule using an inductor element that can detect the bonding reaction between a sample and a biochip by measuring the change of the electrical characteristics of a circuit including the inductance device. The method includes forming a signal conversion unit with at least one inductance device, arranging a biochip in a specified area of the signal conversion unit by immobilizing capturing probe biomolecules on a substrate and measuring electric characteristics of the signal conversion unit, performing a bonding reaction between a sample (such as DNA, RNA, protein, biomolecules, etc.) to be analyzed and the biochip, and measuring the electrical characteristics of the signal conversion unit after the reaction bonding. The result of the bio molecule detection is obtained through an electrical signal, and thus the capability of detecting the bio bonding reaction can be improved in comparison to the conventional apparatus and method.

摘要翻译： 一种使用电感器元件检测生物分子的装置和方法，该电感元件可以通过测量包括电感器件的电路的电特性的变化来检测样品和生物芯片之间的结合反应。 该方法包括：形成具有至少一个电感器件的信号转换单元，通过将捕获探针生物分子固定在基片上并测量信号转换单元的电特性，将生物芯片布置在信号转换单元的指定区域中， 待分析的样品（例如DNA，RNA，蛋白质，生物分子等）和生物芯片，以及测量反应结合后的信号转换单元的电特性。 通过电信号获得生物分子检测的结果，与以往的装置和方法相比，能够提高检测生物结合反应的能力。

公开(公告)号：US20050132798A1

公开(公告)日：2005-06-23

申请号：US11002241

申请日：2004-12-03

申请人： Moon-chul Lee ,  Hyung Choi ,  Seok-jin Kang

发明人： Moon-chul Lee ,  Hyung Choi ,  Seok-jin Kang

IPC分类号： G01C19/56 ,  B81B3/00 ,  B81C1/00 ,  G01C19/5783 ,  H01R13/52 ,  G01P15/14

CPC分类号： G01C19/5769 ,  B81B3/0035 ,  B81B2201/0242 ,  B81C1/00579 ,  B81C1/0092 ,  B81C1/00936 ,  H01R13/52 ,  Y10T29/49002 ,  Y10T29/49005 ,  Y10T29/4902 ,  Y10T74/12 ,  Y10T74/1229

摘要： Method for fabricating a gyroscope including: fabricating a SMS wafer where a first wafer, a metal film, and a second wafer are sequentially stacked; forming a cantilever or a bridge shaped-structure on the relevant portion of the first wafer through the photolithography process; attaching to the surface of the first wafer, a first cap made of glass and having a predetermined space for sealing the movable structure in a vacuum state; separating and removing the metal film and the second wafer from the first wafer; and attaching to the backside of the first wafer, the second cap which is structurally and materially symmetric to the first cap. The SMS wafer is fabricated by depositing the metal film on the second wafer and bonding the first wafer on the metal film using metal paste or material of polymer series. With lower material costs, improvements in performance and characteristics can be achieved.

摘要翻译： 制造陀螺仪的方法，包括：制造顺序堆叠第一晶片，金属膜和第二晶片的SMS晶片; 通过光刻工艺在第一晶片的相关部分上形成悬臂或桥形结构; 附接到第一晶片的表面，由玻璃制成的第一盖，并且具有用于在真空状态下密封可移动结构的预定空间; 从第一晶片分离和去除金属膜和第二晶片; 并且附接到所述第一晶片的所述背面，所述第二盖在所述第一盖结构和物理上对称。 通过在第二晶片上沉积金属膜并使用金属浆料或聚合物系列材料将第一晶片接合在金属膜上来制造SMS晶片。 随着材料成本的降低，可以实现性能和特性的提高。

公开(公告)号：US06720201B2

公开(公告)日：2004-04-13

申请号：US10384495

申请日：2003-03-10

申请人： Eun-sung Lee ,  Chung-woo Kim ,  In-sang Song ,  Jong-seok Kim ,  Moon-chul Lee

发明人： Eun-sung Lee ,  Chung-woo Kim ,  In-sang Song ,  Jong-seok Kim ,  Moon-chul Lee

IPC分类号： H01L2100

CPC分类号： B81B3/0078 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C2201/0107 ,  B81C2201/014 ,  H01H59/0009

摘要： A method for fabricating a MEMS device having a fixing part fixed to a substrate, a connecting part, a driving part, a driving electrode, and contact parts, includes patterning the driving electrode on the substrate; forming an insulation layer on the substrate; patterning the insulation layer and etching a fixing region and a contact region of the insulation layer; forming a metal layer over the substrate; planarizing the metal layer until the insulation layer is exposed; forming a sacrificial layer on the substrate; patterning the sacrificial layer to form an opening exposing a portion of the insulation layer and the metal layer in the fixing region; forming a MEMS structure layer on the sacrificial layer to partially fill the opening, thereby forming sidewalls therein; and selectively removing a portion of the sacrificial layer by etching so that a portion of the sacrificial layer remains in the fixing region.

公开(公告)号：US07452809B2

公开(公告)日：2008-11-18

申请号：US11240771

申请日：2005-10-03

申请人： Moon-chul Lee ,  Woon-bae Kim ,  Jun-sik Hwang ,  Chang-youl Moon

发明人： Moon-chul Lee ,  Woon-bae Kim ,  Jun-sik Hwang ,  Chang-youl Moon

IPC分类号： H01L21/44 ,  H01R43/00

CPC分类号： B81C1/00301 ,  Y10T29/49117

摘要： A fabrication method of a packaging substrate includes the steps of: forming a recess by etching a predetermined area of a lower surface of a substrate; depositing a seed layer on an upper surface of the substrate; in the recess, etching predetermined area(s) of the lower surface of the substrate and forming at least one via hole that reaches the seed layer; and plating the inside of the via hole by using the seed layer, and forming electrode(s) for electrically coupling the upper and lower parts of the substrate. First and second pads coupled to the electrode(s) may be formed on the upper and lower parts of the substrate, respectively. Thus, using the second pads as bonding materials, the packaging process becomes easier, which resultantly simplifies the fabrication process of the packaging substrate and the packaging process.

摘要翻译： 包装基板的制造方法包括以下步骤：通过蚀刻基板的下表面的预定区域来形成凹部; 在基板的上表面上沉积种子层; 在所述凹部中蚀刻所述基板的下表面的预定区域并形成到达所述籽晶层的至少一个通孔; 并且通过使用晶种层对通孔的内部进行电镀，以及形成用于电耦合衬底的上部和下部的电极。 分别连接到电极的第一和第二焊盘分别形成在衬底的上部和下部。 因此，使用第二焊盘作为粘合材料，封装过程变得更容易，从而简化了封装衬底的制造过程和封装过程。

公开(公告)号：US20080072416A1

公开(公告)日：2008-03-27

申请号：US11712526

申请日：2007-03-01

申请人： Young-tack Hong ,  Moon-chul Lee ,  In-sang Song ,  Sang-wook Kwon ,  Chang-won Jung ,  Eun-seok Park

发明人： Young-tack Hong ,  Moon-chul Lee ,  In-sang Song ,  Sang-wook Kwon ,  Chang-won Jung ,  Eun-seok Park

IPC分类号： H01P11/00 ,  H01Q13/00

CPC分类号： H01Q1/2283 ,  H01F17/0033 ,  H01F41/041 ,  H01Q1/362 ,  Y10T29/49016 ,  Y10T29/49018 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A micro antenna and a method of manufacturing the micro antenna are provided. A plurality of holes are formed to penetrate a first substrate. A plurality of vertical conducting parts are formed in the plurality of holes using a conductive material. Horizontal conducting parts are formed on upper and lower surfaces of the first substrate to be electrically connected to the plurality of vertical conducting parts so as to form a 3-dimensional (3-D) coil structure. The first substrate including the 3-D coil structure is bonded to a second substrate and then removed so as to realize the micro antenna.

摘要翻译： 提供微型天线和制造微型天线的方法。 形成多个孔以穿透第一基板。 使用导电材料在多个孔中形成多个垂直导电部件。 水平导电部分形成在第一基板的上表面和下表面上以与多个垂直导电部分电连接，以形成三维（3-D）线圈结构。 将包括3-D线圈结构的第一基板接合到第二基板，然后移除以实现微天线。