Method of forming a fine pattern
    41.
    发明申请
    Method of forming a fine pattern 审中-公开
    形成精细图案的方法

    公开(公告)号:US20080076071A1

    公开(公告)日:2008-03-27

    申请号:US11588496

    申请日:2006-10-28

    IPC分类号: G03F7/00

    摘要: First, second and third layers are formed on a substrate for forming a fine pattern. A first mask pattern having a first space is formed on the third layer. A third layer pattern having a second space exposing the second layer is formed. A first sacrificial layer is formed on the second layer having the third layer pattern. A fourth layer is formed on the first sacrificial layer. A double mask pattern including the first and second mask patterns is formed using the second mask pattern in the second space. A second sacrificial layer is formed on the first sacrificial layer. A sacrificial layer pattern having a third space is formed by removing the double mask pattern, the third layer pattern, and a portion of the first sacrificial layer. An insulation layer pattern is formed by removing a portion of the first and second layers.

    摘要翻译: 首先,在用于形成精细图案的基板上形成第二和第三层。 具有第一空间的第一掩模图案形成在第三层上。 形成具有暴露第二层的第二空间的第三层图案。 在具有第三层图案的第二层上形成第一牺牲层。 在第一牺牲层上形成第四层。 使用第二空间中的第二掩模图案形成包括第一和第二掩模图案的双掩模图案。 在第一牺牲层上形成第二牺牲层。 通过去除双掩模图案,第三层图案和第一牺牲层的一部分来形成具有第三空间的牺牲层图案。 通过去除第一层和第二层的一部分来形成绝缘层图案。

    Method for fabricating a semiconductor device
    42.
    发明授权
    Method for fabricating a semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号:US07001817B2

    公开(公告)日:2006-02-21

    申请号:US10696417

    申请日:2003-10-29

    IPC分类号: H01L21/336

    摘要: A method for fabricating a semiconductor device, including forming a gate insulating film and a gate electrode film on a semiconductor substrate, and patterning the gate electrode film to form a gate electrode. A portion of the gate insulating film is removed to form an undercut region beneath the gate electrode. A buffer silicon film is formed over an entire surface of the resultant substrate to cover the gate electrode and to fill the undercut region. The buffer silicon film is selectively oxidized to form a buffer silicon oxide film.

    摘要翻译: 一种制造半导体器件的方法,包括在半导体衬底上形成栅极绝缘膜和栅极电极膜,以及对栅电极膜进行构图以形成栅电极。 去除栅极绝缘膜的一部分以在栅极电极下方形成底切区域。 在所得基板的整个表面上形成缓冲硅膜以覆盖栅电极并填充底切区域。 缓冲硅膜被选择性地氧化以形成缓冲氧化硅膜。

    Methods of forming capacitor structures including L-shaped cavities and related structures
    43.
    发明申请
    Methods of forming capacitor structures including L-shaped cavities and related structures 有权
    形成电容器结构的方法包括L形腔和相关结构

    公开(公告)号:US20050112819A1

    公开(公告)日:2005-05-26

    申请号:US10977385

    申请日:2004-10-29

    摘要: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

    摘要翻译: 形成电容器结构的方法可以包括在衬底上形成绝缘层,在绝缘层上形成第一电容器电极,在第一电容器电极的部分上形成电容器电介质层,以及在电容器电介质层上形成第二电容器电极, 电容器介电层位于第一和第二电容器电极之间。 更具体地,第一电容器电极可以在其中限定空腔,其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。 还讨论了相关结构。

    Non-Volatile Memory Devices
    44.
    发明申请
    Non-Volatile Memory Devices 有权
    非易失性存储器件

    公开(公告)号:US20090261405A1

    公开(公告)日:2009-10-22

    申请号:US12491529

    申请日:2009-06-25

    IPC分类号: H01L29/792

    CPC分类号: H01L21/28282

    摘要: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

    摘要翻译: 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层,隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

    METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
    45.
    发明申请
    METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
    形成具有其部分的下降线宽度的金属氧化物层图案的方法和使用其制造半导体器件的方法

    公开(公告)号:US20080199975A1

    公开(公告)日:2008-08-21

    申请号:US12032018

    申请日:2008-02-15

    IPC分类号: H01L21/18 H01L21/3065

    摘要: Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern.

    摘要翻译: 本文提供了在衬底上形成金属氧化物层图案的方法,包括在衬底上提供初步金属氧化物层; 蚀刻初始金属氧化物层以提供初步金属氧化物层图案,其中预备金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 并且以使得预备金属氧化物层的下部的线宽减小的方式蚀刻初步金属氧化物层图案以形成金属氧化物层图案。 本发明还提供了制造半导体器件的方法,包括在衬底上形成金属氧化物层和第一导电层; 蚀刻金属氧化物层以提供初步金属氧化物层图案,其中初始金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 蚀刻第一导电层以提供第一导电层图案; 并且蚀刻初步金属氧化物层图案以提供金属氧化物层图案,以便减小初步金属氧化物层图案的下部的线宽度。

    Non-volatile memory devices and methods of manufacturing the same
    46.
    发明申请
    Non-volatile memory devices and methods of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号:US20080150008A1

    公开(公告)日:2008-06-26

    申请号:US12004985

    申请日:2007-12-21

    IPC分类号: H01L29/792 H01L21/28

    CPC分类号: H01L21/28282

    摘要: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

    摘要翻译: 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层,隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

    Methods of forming capacitor structures including L-shaped cavities
    47.
    发明授权
    Methods of forming capacitor structures including L-shaped cavities 有权
    形成电容器结构的方法包括L形腔

    公开(公告)号:US07312130B2

    公开(公告)日:2007-12-25

    申请号:US10977385

    申请日:2004-10-29

    IPC分类号: H01L21/20

    摘要: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

    摘要翻译: 形成电容器结构的方法可以包括在衬底上形成绝缘层,在绝缘层上形成第一电容器电极,在第一电容器电极的部分上形成电容器电介质层,以及在电容器电介质层上形成第二电容器电极, 电容器介电层位于第一和第二电容器电极之间。 更具体地,第一电容器电极可以在其中限定空腔,其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。 还讨论了相关结构。

    Method of processing semiconductor substrate responsive to a state of chamber contamination
    48.
    发明申请
    Method of processing semiconductor substrate responsive to a state of chamber contamination 审中-公开
    响应室污染状态处理半导体衬底的方法

    公开(公告)号:US20070020780A1

    公开(公告)日:2007-01-25

    申请号:US11370478

    申请日:2006-03-07

    IPC分类号: H01L21/66 G01R31/26

    CPC分类号: H01L22/00

    摘要: In one embodiment, a method of processing a semiconductor substrate includes measuring a state of a processing chamber contamination before processing each semiconductor substrate. A process condition is then changed responsive to the state of chamber contamination to compensate for an influence of the state of chamber contamination on the process condition. If the change in process condition is outside of predetermined margin, a warning may be generated and the process may be stopped.

    摘要翻译: 在一个实施例中,处理半导体衬底的方法包括在处理每个半导体衬底之前测量处理室污染的状态。 响应于室污染的状态来改变工艺条件以补偿室污染状态对工艺条件的影响。 如果处理条件的改变超出预定余量,则可能产生警告并且可以停止处理。

    Method for forming a self aligned contact in a semiconductor device
    49.
    发明授权
    Method for forming a self aligned contact in a semiconductor device 有权
    在半导体器件中形成自对准接触的方法

    公开(公告)号:US06177320B1

    公开(公告)日:2001-01-23

    申请号:US09226961

    申请日:1999-01-08

    IPC分类号: H01L21336

    摘要: A self aligned contact pad in a semiconductor device and a method for forming the self aligned contact pad are disclosed. A bit line contact pad and a storage node contact pad are simultaneously formed by using a photoresist layer pattern having a T-shaped opening including at least two contact regions. An etch stopping layer is formed over a semiconductor substrate and over a transistor. An interlayer dielectric layer is then formed over the etch stopping layer. Next, the interlayer dielectric layer is planarized to have a planar top surface. A mask pattern having a T-shaped opening is then formed over the interlayer dielectric layer, exposing the active region and a portion of the inactive region. The interlayer dielectric layer and etch stopping layer are sequentially etched to reveal a top surface of the semiconductor substrate using the mask pattern, thereby forming a self aligned contact opening exposing a top surface of the semiconductor substrate. The mask pattern is then removed. A conductive layer is formed in the self aligned contact opening and over the interlayer dielectric layer. The conductive layer and the interlayer dielectric layer are planarization-etched to reveal a top surface of the gate mask, thereby forming at least two contact pads.

    摘要翻译: 公开了半导体器件中的自对准接触焊盘和用于形成自对准接触焊盘的方法。 通过使用具有包括至少两个接触区域的T形开口的光致抗蚀剂层图案,同时形成位线接触焊盘和存储节点接触焊盘。 在半导体衬底上并在晶体管上形成蚀刻停止层。 然后在蚀刻停止层上形成层间电介质层。 接下来,层间绝缘层被平坦化以具有平坦的顶表面。 然后在层间电介质层上形成具有T形开口的掩模图案,暴露有源区和一部分非活性区。 依次蚀刻层间电介质层和蚀刻停止层,以使用掩模图案露出半导体衬底的顶表面,从而形成暴露半导体衬底的顶表面的自对准接触开口。 然后去除掩模图案。 导电层形成在自对准接触开口中以及层间电介质层之上。 对导电层和层间电介质层进行平面蚀刻以露出栅极掩模的顶表面,从而形成至少两个接触焊盘。