公开(公告)号：US07851878B2

公开(公告)日：2010-12-14

申请号：US12507504

申请日：2009-07-22

申请人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

摘要翻译： 磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体， 写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

公开(公告)号：US07729160B2

公开(公告)日：2010-06-01

申请号：US11616969

申请日：2006-12-28

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hye-Jin Kim

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC分类号： G11C11/00

CPC分类号： G11C29/808 ,  G11C29/02 ,  G11C29/027 ,  G11C29/787 ,  G11C29/804 ,  G11C29/846

摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.

摘要翻译： 相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量 控制信号。

公开(公告)号：US07724560B2

公开(公告)日：2010-05-25

申请号：US12107985

申请日：2008-04-23

申请人： Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh ,  Joon-Min Park

发明人： Sang-Beom Kang ,  Woo-Yeong Cho ,  Hyung-Rok Oh ,  Joon-Min Park

IPC分类号： G11C5/06

CPC分类号： G11C13/003 ,  G11C11/14 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

摘要： A nonvolatile memory device includes multiple first bit lines extending in a first direction, multiple word lines formed on the first bit lines and extending in a second direction different from the first direction, and multiple second bit lines, formed on the word lines and extending in the first direction. The nonvoliative memory device also includes multiple twin memory cells, each of which includes a first memory cell coupled between a first bit line and a word line and a second memory cell coupled between the word line and a second bit line. The first and second memory cells store different data.

摘要翻译： 非易失性存储器件包括沿第一方向延伸的多个第一位线，形成在第一位线上并在与第一方向不同的第二方向上延伸的多个字线以及形成在字线上并在字线上延伸的多个第二位线 第一个方向。 非易失性存储器件还包括多个双存储器单元，每个存储单元包括耦合在第一位线和字线之间的第一存储器单元和耦合在字线和第二位线之间的第二存储单元。 第一和第二存储单元存储不同的数据。

公开(公告)号：US20090225590A1

公开(公告)日：2009-09-10

申请号：US12453420

申请日：2009-05-11

申请人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

发明人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

公开(公告)号：US07582941B2

公开(公告)日：2009-09-01

申请号：US11480242

申请日：2006-06-30

申请人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Choong-Keun Kwak

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L27/224 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.

摘要翻译： 磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。 磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体， 写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

公开(公告)号：US07570511B2

公开(公告)日：2009-08-04

申请号：US11755329

申请日：2007-05-30

申请人： Woo-Yeong Cho ,  Sang-Beom Kang ,  Du-Eung Kim

发明人： Woo-Yeong Cho ,  Sang-Beom Kang ,  Du-Eung Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0023 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor memory device includes a plurality of cell array layers including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction that intersects the first direction, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. Each of the word lines has a word line position, each of the bit lines has a bit line position, and each of the memory cells includes a variable resistance device in series with a diode. The cell array layers are arranged in layers in a third direction that is perpendicular to the first and second directions. The bit lines of each of the cell array layers having a same bit line position are connected to a common column selector transistor, or the word lines of the cell array layers having a same word line position are connected to a common word line driver.

摘要翻译： 半导体存储器件包括多个单元阵列层，包括沿第一方向延伸的多个字线，沿与第一方向相交的第二方向延伸的多个位线，以及设置在第一方向的交点处的多个存储单元 字线和位线。 每个字线具有字线位置，每个位线具有位线位置，并且每个存储单元包括与二极管串联的可变电阻器件。 单元阵列层在垂直于第一和第二方向的第三方向上排列成层。 具有相同位线位置的每个单元阵列层的位线连接到公共列选择晶体管，或者具有相同字线位置的单元阵列层的字线连接到公共字线驱动器。

公开(公告)号：US07499316B2

公开(公告)日：2009-03-03

申请号：US11723354

申请日：2007-03-19

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Yu-Hwan Ro ,  Joon-Yong Choi ,  Beak-Hyung Cho ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Yu-Hwan Ro ,  Joon-Yong Choi ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.

摘要翻译： 公开了一种相变存储器件。 其包括存储单元阵列，其包括相对于相变材料编程的多个存储器单元，以及写入驱动器电路，其被配置为向所选存储单元提供置位电流和复位电流。 写驱动器电路包括配置成提供设定电流的设定电流驱动器和被配置为提供复位电流的复位电流驱动器。

公开(公告)号：US20080303016A1

公开(公告)日：2008-12-11

申请号：US12196137

申请日：2008-08-21

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L45/00

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

公开(公告)号：US07427531B2

公开(公告)日：2008-09-23

申请号：US11324112

申请日：2005-12-30

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L21/06

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

公开(公告)号：US20080101131A1

公开(公告)日：2008-05-01

申请号：US11790146

申请日：2007-04-24

申请人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

发明人： Kwang-Jin Lee ,  Sang-Beom Kang ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Woo-Yeong Cho

IPC分类号： G11C7/06

CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/1006 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2211/5647

摘要： Embodiments of the invention provide devices or methods that include a status bit representing an inversion of stored data. New data is written to selected cells, the new data is selectively inverted, and the status bit is selectively toggled, based on a comparison between pre-existing data and new data associated with a write command. A benefit of embodiments of the invention is that fewer memory cells must be activated in many instances (when compared to conventional art approaches). Moreover, embodiments of the invention may also reduce the average amount of activation current required to write to variable resistive memory devices and other memory device types.

摘要翻译： 本发明的实施例提供了包括表示存储数据的反转的状态位的设备或方法。 将新数据写入所选择的单元，根据预先存在的数据与与写命令相关联的新数据之间的比较，选择性地反转新数据并选择性地切换状态位。 本发明的实施例的优点在于，在许多情况下（与传统技术方法相比），必须激活更少的存储器单元。 此外，本发明的实施例还可以减少写入可变电阻存储器件和其他存储器件类型所需的平均激活电流量。