公开(公告)号：US20120306019A1

公开(公告)日：2012-12-06

申请号：US13571521

申请日：2012-08-10

申请人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

发明人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

IPC分类号： H01L27/088

CPC分类号： H01L21/823468 ,  H01L21/28176 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/78

摘要： A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.

摘要翻译： 半导体器件包括位于衬底上的第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层，其中所述第二界面氧化物层 第二FET比第一FET的第一界面氧化物层厚; 以及位于与第二FET相邻的衬底中的凹部。

公开(公告)号：US20120248537A1

公开(公告)日：2012-10-04

申请号：US13073110

申请日：2011-03-28

申请人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

发明人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L21/823468 ,  H01L21/28176 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/78

摘要： A method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.

摘要翻译： 一种用于形成半导体器件的方法包括在衬底上形成第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层; 封装第一FET的第一界面氧化物层; 以及执行第二FET的第二界面氧化物层的侧向氧化，其中第二FET的第二界面氧化物层的侧向氧化将位于第二FET下面的衬底的一部分转换为另外的界面氧化物。

公开(公告)号：US08716807B2

公开(公告)日：2014-05-06

申请号：US13571521

申请日：2012-08-10

申请人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

发明人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

IPC分类号： H01L21/70

CPC分类号： H01L21/823468 ,  H01L21/28176 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/78

摘要： A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET.

摘要翻译： 半导体器件包括位于衬底上的第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层，其中所述第二界面氧化物层 第二FET比第一FET的第一界面氧化物层厚; 以及位于与第二FET相邻的衬底中的凹部。

公开(公告)号：US08242560B2

公开(公告)日：2012-08-14

申请号：US12688347

申请日：2010-01-15

申请人： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

发明人： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.

摘要翻译： 提供了一种半导体器件，其在一个实施例中包括在电介质表面之上的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区， 漏区存在于半导体鳍结构的相对端。 具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。 至少一个栅极导体层与高k栅极电介质层直接接触。 还提供了一种形成上述装置的方法。

公开(公告)号：US06770501B2

公开(公告)日：2004-08-03

申请号：US10277835

申请日：2002-10-23

申请人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

发明人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

IPC分类号： H01L213205

CPC分类号： H01L21/76224 ,  H01L21/3003 ,  H01L21/823481

摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.

摘要翻译： 半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。 板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。 氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。 后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此 允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。

公开(公告)号：US06521977B1

公开(公告)日：2003-02-18

申请号：US09489277

申请日：2000-01-21

申请人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

发明人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

IPC分类号： H01L2358

CPC分类号： H01L21/76224 ,  H01L21/3003 ,  H01L21/823481

摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.

摘要翻译： 半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。 板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。 氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。 后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此 允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。

公开(公告)号：US20110175163A1

公开(公告)日：2011-07-21

申请号：US12688347

申请日：2010-01-15

申请人： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

发明人： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.

摘要翻译： 提供了一种半导体器件，其在一个实施例中包括在电介质表面上方的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区， 漏区存在于半导体鳍结构的相对端。 具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。 至少一个栅极导体层与高k栅极电介质层直接接触。 还提供了一种形成上述装置的方法。

公开(公告)号：US06603181B2

公开(公告)日：2003-08-05

申请号：US09760621

申请日：2001-01-16

申请人： Paul M. Solomon ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kathryn W. Guarini ,  Fenton R. McFeely ,  Huiling Shang ,  John J. Yourkas

发明人： Paul M. Solomon ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kathryn W. Guarini ,  Fenton R. McFeely ,  Huiling Shang ,  John J. Yourkas

IPC分类号： H01L2976

CPC分类号： H01L29/517 ,  H01L21/263 ,  H01L21/28079 ,  H01L29/495 ,  Y10S438/91

摘要： A MOS structure processed to have a semiconductor-dielectric interface that is passivated to reduce the interface state density. An example is a MOSFET having a gate dielectric on which an electrode is present that is substantially impervious to molecular hydrogen, but sufficiently thin to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused therethrough into an underlying semiconductor-dielectric interface. Atomic hydrogen diffusion can be achieved by subjecting such an electrode to hydrogen plasma, forming the electrode of an aluminum-tungsten alloy in the presence of hydrogen, and implanting atomic hydrogen into the electrode. The latter two techniques are each followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.

摘要翻译： 被处理成具有钝化的半导体 - 电介质界面以降低界面态密度的MOS结构。 一个例子是具有栅电介质的MOSFET，其上存在基本上不透分子氢的电极，但是足够薄以能够透过原子氢，使原子氢能够通过其扩散到下面的半导体介电界面中。 原子氢扩散可以通过使这样的电极经受氢等离子体，在氢的存在下形成铝 - 钨合金的电极，并将原子氢注入到电极中来实现。 后两种技术之后各自进行退火以使原子氢扩散通过电极并进入半导体 - 电介质界面。

公开(公告)号：US07871869B2

公开(公告)日：2011-01-18

申请号：US12543679

申请日：2009-08-19

申请人： Eduard A. Cartier ,  Steven J. Koester ,  Kingsuk Maitra ,  Amlan Majumdar ,  Renee T. Mo

发明人： Eduard A. Cartier ,  Steven J. Koester ,  Kingsuk Maitra ,  Amlan Majumdar ,  Renee T. Mo

IPC分类号： H01L21/00

CPC分类号： H01L29/6659 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78696

摘要： An extremely-thin silicon-on-insulator transistor is provided that includes a buried oxide layer above a substrate, a silicon layer above the buried oxide layer, a gate stack on the silicon layer, a nitride liner on the silicon layer and adjacent to the gate stack, an oxide liner on and adjacent to the nitride liner, and raised source/drain regions. The gate stack includes a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. Each of the raised source/drain regions has a first part comprising a portion of the silicon layer, a second part adjacent to parts of the oxide liner and the nitride liner, and a third part above the second part. Also provided is a method for fabricating an extremely-thin silicon-on-insulator transistor.

摘要翻译： 提供了一种极薄的绝缘体上硅晶体管，其包括衬底上的掩埋氧化物层，掩埋氧化物层上方的硅层，硅层上的栅极堆叠，硅层上的氮化物衬垫， 栅堆叠，氮化物衬垫上并与其相邻的氧化物衬垫，以及升高的源/漏区。 栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。 凸起的源极/漏极区域中的每一个具有包括硅层的一部分的第一部分，与氧化物衬垫和氮化物衬垫的部分相邻的第二部分，以及在第二部分上方的第三部分。 还提供了制造极薄的绝缘体上硅晶体管的方法。

公开(公告)号：US06803266B2

公开(公告)日：2004-10-12

申请号：US10249184

申请日：2003-03-20

申请人： Paul M. Solomon ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kathryn W. Guarini ,  Fenton R. McFeely ,  Huiling Shang ,  John J. Yourkas

发明人： Paul M. Solomon ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kathryn W. Guarini ,  Fenton R. McFeely ,  Huiling Shang ,  John J. Yourkas

IPC分类号： H01L21336

CPC分类号： H01L29/517 ,  H01L21/263 ,  H01L21/28079 ,  H01L29/495 ,  Y10S438/91

摘要： A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface. Three general approaches are encompassed: forming an aluminum-tungsten electrode stack in the presence of hydrogen so as to store atomic hydrogen between the tungsten and aluminum layers, followed by an anneal to cause the atomic hydrogen to diffuse through the tungsten layer and into the interface; subjecting a tungsten electrode to hydrogen plasma, during which atomic hydrogen diffuses through the electrode and into the semiconductor-dielectric interface; and implanting atomic hydrogen into tungsten electrode, followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.

摘要翻译： 一种用于钝化MOS结构的半导体 - 电介质界面以将界面态密度降低到非常低的水平的方法。 具体的示例是具有钨电极的MOSFET，其过去已经阻止下面的半导体 - 电介质界面的钝化达到足以将界面态密度降低到小于5×10 10 / cm 2 -eV的程度。 虽然基本上不透分子氢，但是显示出薄钨层可以透过原子氢，使原子氢能够通过钨电极扩散到下面的半导体 - 电介质界面。 包括三种一般方法：在氢的存在下形成铝 - 钨电极堆叠，以便在钨和铝层之间存储原子氢，随后进行退火，使原子氢扩散通过钨层并进入界面 ; 使钨电极经受氢等离子体，其中原子氢通过电极扩散并进入半导体 - 电介质界面; 并将原子氢注入钨电极中，随后进行退火，使原子氢扩散通过电极并进入半导体 - 电介质界面。