公开(公告)号：US20120167029A1

公开(公告)日：2012-06-28

申请号：US13413759

申请日：2012-03-07

Applicant: John M. Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woltgens

Inventor： John M. Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woltgens

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5072

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract translation: 一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。 布局单元接收表示网格和字形格式的部分的电路描述。 检查单元检查设计的网格和字形部分。 精心设计单元从检查的设计生成目标布局。 数据准备单元准备掩模制作的目标布局。 模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

公开(公告)号：US20120149200A1

公开(公告)日：2012-06-14

申请号：US12966432

申请日：2010-12-13

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/28035 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/78

Abstract: A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

Abstract translation: 一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。 在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。 在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。 所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。

公开(公告)号：US08176444B2

公开(公告)日：2012-05-08

申请号：US12426475

申请日：2009-04-20

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US07865864B2

公开(公告)日：2011-01-04

申请号：US12024188

申请日：2008-02-01

Applicant: Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

Inventor： Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.

Abstract translation: 描述了提供电驱动光学邻近校正的方法。 在一个实施例中，存在执行电驱动光学邻近校正的方法。 在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。 在掩模布局上运行光刻仿真。 从掩模布局的每层的光刻模拟的输出中提取电特性。 确定提取的电特性是否与目标电特性一致。 响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。

公开(公告)号：US07627836B2

公开(公告)日：2009-12-01

申请号：US11164044

申请日：2005-11-08

Applicant: James A. Culp ,  Lars W. Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen L. Runyon ,  Patrick M. Williams

Inventor： James A. Culp ,  Lars W. Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen L. Runyon ,  Patrick M. Williams

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

Abstract translation: 基于使用光学邻近校正技术的方法，在芯片制造之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

公开(公告)号：US20090282380A1

公开(公告)日：2009-11-12

申请号：US12117761

申请日：2008-05-09

Applicant: Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

Abstract translation: 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

公开(公告)号：US20090210834A1

公开(公告)日：2009-08-20

申请号：US12031734

申请日：2008-02-15

Applicant: Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

IPC: G06F9/45

CPC classification number: G06F17/5081

Abstract: IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.

Abstract translation: 公开了使用周界密度到电特性相关性的IC芯片设计建模。 在一个实施例中，一种方法可以包括确定集成电路（IC）芯片设计的多个区域的每个区域内的导电结构的周边密度; 将基于IC芯片设计的IC芯片的相应区域中的测量电特性与周围密度相关联; 并根据相关性对IC芯片设计进行建模。

公开(公告)号：US20090199151A1

公开(公告)日：2009-08-06

申请号：US12024188

申请日：2008-02-01

Applicant: Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

Inventor： Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.

Abstract translation: 描述了提供电驱动光学邻近校正的方法。 在一个实施例中，存在执行电驱动光学邻近校正的方法。 在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。 在掩模布局上运行光刻仿真。 从掩模布局的每层的光刻模拟的输出中提取电特性。 确定提取的电特性是否与目标电特性一致。 响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。

公开(公告)号：US20090193387A1

公开(公告)日：2009-07-30

申请号：US12019125

申请日：2008-01-24

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Alan E. Rosenbluth

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Alan E. Rosenbluth

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/44 ,  G03F1/68

Abstract: A method is provided for designing a mask that includes the use of a pixel-based simulation of a lithographic process model, in which test structures are designed for determining numerical and discretization errors associated with the pixel grid as opposed to other model inaccuracies. The test structure has a plurality of rows of the same sequence of features, but each row is offset from other rows along an x-direction by a multiple of a minimum step size, such as used in modifying masks during optical proximity correction. The images for each row are simulated with a lithographic model that uses the selected pixel-grid size and the differences between row images are compared. If the differences between rows exceed or violate a predetermined criterion, the pixel grid size may be modified to minimize discretization and/or numerical errors due to the choice of pixel grid size.

Abstract translation: 提供了一种用于设计包括使用光刻处理模型的基于像素的仿真的掩模的方法，其中测试结构被设计用于确定与像素网格相关的数值和离散化误差，而不是其他模型不准确。 测试结构具有相同序列特征的多行，但是每一行都沿x方向与其他行偏移最小步长的倍数，例如在光学邻近校正期间用于修改掩模。 使用所选择的像素网格大小的光刻模型来模拟每行的图像，并比较行图像之间的差异。 如果行之间的差异超过或违反预定标准，则可以修改像素网格大小以使由于像素网格大小的选择而导致的离散化和/或数值误差最小化。

公开(公告)号：US07536664B2

公开(公告)日：2009-05-19

申请号：US10917193

申请日：2004-08-12

Applicant: John M. Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woltgens

Inventor： John M. Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woltgens

IPC: G06F17/50 ,  G06F19/00

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5072

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract translation: 一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。 布局单元接收表示网格和字形格式的部分的电路描述。 检查单元检查设计的网格和字形部分。 精心设计单元从检查的设计生成目标布局。 数据准备单元准备掩模制作的目标布局。 模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。