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公开(公告)号：US09928208B2
公开(公告)日：2018-03-27
申请号：US14700860
申请日：2015-04-30
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku
IPC: G06F13/42 , G06F13/364 , H04L12/64
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/42 , G06F13/4282 , H04L12/6418
Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first signaling in accordance with I2C bus protocols, and the first signaling may be combined with second signaling to obtain combined signaling for transmission on an I2C bus. Secondary data may be encoded in the second signaling with the combined signaling remaining compatible with the I2C bus protocols. The second signaling may modulate a voltage level of at least one signal in the first signaling. The second signaling may pulse-width modulate a clock signal transmitted on the I2C bus. The second signaling may modify a start condition between bytes transmitted on the I2C bus. The second signaling may add a plurality of short pulses to a clock signal transmitted in the first signaling.
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42.发明申请公开(公告)号：US20180027174A1
公开(公告)日：2018-01-25
申请号：US15214308
申请日：2016-07-19
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku
CPC classification number: H04N5/23216 , G06F3/04847 , G06F13/36 , G06F13/40 , G06F13/4282 , H04N1/00 , H04N5/23206 , H04N5/23225 , H04N5/23245 , H04N5/2353
Abstract: Systems, methods, and apparatus for signaling reconfiguration of an imaging device are disclosed. In one example, configuration changes in an imaging device are signaled by reconfiguring an operation of the imaging device, generating a first data frame after reconfiguring the operation of the imaging device, where the first data frame includes image data and embedded metadata associated with the image data, modifying the embedded metadata when the first data frame is the first-generated data frame generated after reconfiguring the operation of the imaging device, including modifying an element of the metadata that is associated with a feature of the imaging device unaffected by the reconfiguring, and transmitting the first data frame over an image data communication link after modifying the embedded metadata.
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公开(公告)号：US09853806B2
公开(公告)日：2017-12-26
申请号：US15262280
申请日：2016-09-12
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku
CPC classification number: H04L7/0087 , H04L7/0008 , H04L7/0276 , H04L7/033 , H04L7/04 , H04L25/14
Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.
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公开(公告)号：US09842020B2
公开(公告)日：2017-12-12
申请号：US14949290
申请日：2015-11-23
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku
IPC: H04L25/03 , G06F11/10 , H04L1/00 , H04L27/38 , H03M13/03 , H04L1/24 , H04L25/02 , H04L25/14 , H04L25/493 , H03M5/00 , H03M13/00
CPC classification number: G06F11/1004 , H03M5/00 , H03M13/03 , H03M13/63 , H04L1/004 , H04L1/0041 , H04L1/0061 , H04L1/245 , H04L7/033 , H04L25/0264 , H04L25/0272 , H04L25/03286 , H04L25/14 , H04L25/493 , H04L27/38
Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.
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公开(公告)号：US09735948B2
公开(公告)日：2017-08-15
申请号：US14875592
申请日：2015-10-05
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku
CPC classification number: H04L7/0008 , H04L7/0087 , H04L7/0276 , H04L7/033 , H04L7/0331 , H04L25/0272 , H04L25/14
Abstract: System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.
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Patent Agency Ranking
公开(公告)号：US09639499B2
公开(公告)日：2017-05-02
申请号：US14302359
申请日：2014-06-11
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Joseph Cheung
IPC: G06F13/42 , G06F13/364 , H04L7/033
CPC classification number: G06F13/4291 , G06F13/364 , G06F13/4282 , G06F13/4295 , H04L7/0331
Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.
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公开(公告)号：US20170117979A1
公开(公告)日：2017-04-27
申请号：US15253020
申请日：2016-08-31
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley
CPC classification number: H04J3/0605 , G06F13/42 , G06F13/4282 , G06F21/85 , H04L1/0061 , H04L9/0662 , H04L25/03866 , H04L45/74 , Y02D10/14 , Y02D10/151
Abstract: System, methods and apparatus are described that support multimode operation of a data communication interface. A method includes initializing a scrambler with a first pseudo-random binary sequence (PRBS) seed word after receiving a first sync word, the first sync word preceding a first packet, using the scrambler and the first PRBS seed word to scramble a first copy of a packet header that succeeds the first sync word in the first packet, initializing the scrambler with a second PRBS seed word after scrambling the first copy of the packet header, the second sync word succeeding the first copy of the packet header in the first packet, using the scrambler and the second PRBS seed word to scramble a second copy of the packet header that succeeds the second sync word in the first packet.
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公开(公告)号：US09621332B2
公开(公告)日：2017-04-11
申请号：US15084171
申请日：2016-03-29
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku
CPC classification number: H04L7/0045 , G06F1/12 , H03K5/13 , H03K5/133 , H03K5/1534 , H04L7/0037 , H04L7/0087 , H04L7/033 , H04L25/49
Abstract: A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.
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49.发明授权Method and apparatus to enable multiple masters to operate in a single master bus architecture 有权使多个主机能够在单个主总线架构中运行的方法和装置公开(公告)号：US09519603B2
公开(公告)日：2016-12-13
申请号：US14480540
申请日：2014-09-08
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , Richard Dominic Wietfeldt , George Alan Wiley
IPC: G06F13/378 , G06F13/36 , G06F13/24 , G06F13/362
CPC classification number: G06F13/378 , G06F13/24 , G06F13/36 , G06F13/362 , G06F2213/3602
Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
Abstract translation: 为了通过支持单个主器件的总线架构来容纳多个主器件，为非激活主器件提供了通过共享的单线IRQ总线触发IRQ信号的机制。 然后当前主机通过共享数据总线轮询其他无效主设备，以确定哪个无效主设备正在断言IRQ信号。 当识别出断言无效的主设备时，当前的主设备将数据总线的控制权授予新的主设备，从而使非活动主设备成为新的主主设备。
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50.发明申请METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE 审中-公开使用多个主机在单个主总线架构中运行的方法和装置公开(公告)号：US20160217090A1
公开(公告)日：2016-07-28
申请号：US15087535
申请日：2016-03-31
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , Richard Dominic Wietfeldt , George Alan Wiley
IPC: G06F13/364 , G06F13/42 , G06F13/26
CPC classification number: G06F13/364 , G06F13/24 , G06F13/26 , G06F13/362 , G06F13/4256 , G06F13/426
Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
Abstract translation: 为了通过支持单个主设备的总线架构来容纳多个主机，为非活动主设备提供了一种机制来断言带内IRQ。 然后当前主机通过共享数据总线轮询其他无效的主设备，以确定哪个非活动主设备正在断言IRQ。 当识别出断言无效的主设备时，当前的主设备将数据总线的控制权授予新的主设备，从而使非活动主设备成为新的主主设备。
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