公开(公告)号：US20120104507A1

公开(公告)日：2012-05-03

申请号：US12938457

申请日：2010-11-03

申请人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

发明人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828

摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

摘要翻译： 一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于 厚度减小 在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

公开(公告)号：US07919379B2

公开(公告)日：2011-04-05

申请号：US11852906

申请日：2007-09-10

申请人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

发明人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

IPC分类号： H01L21/00 ,  H01L21/336

CPC分类号： H01L21/31116 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

公开(公告)号：US20090081836A1

公开(公告)日：2009-03-26

申请号：US11860127

申请日：2007-09-24

申请人： Yaocheng Liu ,  Qiqing C. Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

发明人： Yaocheng Liu ,  Qiqing C. Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

IPC分类号： H01L21/265 ,  H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.

摘要翻译： 提供了在源极和漏极区域中形成晶体Si：C的方法。 在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。 在源极和漏极区域中进行前置放电，随后进行碳注入。 源区和漏区的上部包括硅，锗和/或碳的无定形混合物。 沉积抗反射层以增强激光束到硅衬底中的吸收。 激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。 控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持了半导体结构的结构完整性。

公开(公告)号：US20090065817A1

公开(公告)日：2009-03-12

申请号：US11852906

申请日：2007-09-10

申请人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

发明人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

IPC分类号： H01L21/311 ,  H01L29/78

CPC分类号： H01L21/31116 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在所述FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

公开(公告)号：US20090001470A1

公开(公告)日：2009-01-01

申请号：US11768257

申请日：2007-06-26

申请人： Brent A. Anderson ,  Edward J. Nowak ,  Kathryn T. Schonenberg

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Kathryn T. Schonenberg

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

摘要： In a method of fabricating a semiconductor finFET transistor for an integrated circuit chip comprising 1) the formation of at least one fin body on the surface of a substrate and 2) the formation of a gate on said fin body in a non-orthogonal orientation relative to the body thereby creating acute angle regions at the crossover of the gate on the body, and 3) the formation of a protective material in the acute angle regions so as to prevent damage to the gate during subsequent fabrication steps. The structure of the finFET transistor comprises such a transistor with protective material in the acute angle regions at the crossover of the gate on the body.

摘要翻译： 一种用于制造用于集成电路芯片的半导体finFET晶体管的方法，包括：1）在衬底的表面上形成至少一个翅片体，以及2）在所述翅片体上以非正交取向相对形成栅极 从而在主体上的栅极交叉处产生锐角区域，以及3）在锐角区域中形成保护材料，以防止在随后的制造步骤期间损坏栅极。 finFET晶体管的结构包括在主体上的栅极交叉处的锐角区域中的这种具有保护材料的晶体管。

公开(公告)号：US20080265282A1

公开(公告)日：2008-10-30

申请号：US11741836

申请日：2007-04-30

申请人： Oleg Gluschenkov ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Oleg Gluschenkov ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L31/11 ,  H01L21/331 ,  H01L31/117 ,  H01L31/00

CPC分类号： H01L29/66242 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

摘要： Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

摘要翻译： 公开了一种改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管），其具有窄的基本上无间隙的SIC基座，其外部基极具有最小的重叠。 此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。 因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。

公开(公告)号：US20080128861A1

公开(公告)日：2008-06-05

申请号：US11555906

申请日：2006-11-02

申请人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L29/73

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

摘要翻译： 提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。 所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。 富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。 然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

公开(公告)号：US06780695B1

公开(公告)日：2004-08-24

申请号：US10249563

申请日：2003-04-18

申请人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

发明人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

IPC分类号： H01L218238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

摘要翻译： 提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。 该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。 然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。 然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。 然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。