公开(公告)号：US09489323B2

公开(公告)日：2016-11-08

申请号：US14182986

申请日：2014-02-18

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract translation: 存储器模块包括数据接口，该数据接口包括多个数据线和耦合在数据接口和到一个或多个存储器的数据路径之间的多个可配置开关。 可以通过启用或禁用可配置开关的不同子集来配置内存模块的有效宽度。 可配置开关可以由手动开关，存储器模块上的缓冲器，外部存储器控制器或存储器模块上的存储器来控制。

公开(公告)号：US20150103876A1

公开(公告)日：2015-04-16

申请号：US14575985

申请日：2014-12-18

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Kambiz Kaviani ,  Aliazam Abbasfar

IPC: H04L25/03

CPC classification number: H04L25/03949 ,  H03K5/24

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract translation: 部分响应判决反馈均衡器（PrDFE）包括至少包括第一和第二比较器的接收器，该第一和第二比较器可操作以将表示符号序列的输入信号与相应阈值进行比较，并且分别产生第一和第二接收器输出。 提供第一选择级，以根据第一定时信号在第一比较器输出和第一解析符号之间选择（a），以及（b）根据第一定时信号在第二比较器输出和第一解析符号之间选择 产生相应的第一和第二选择输出。 第二选择阶段根据选择信号在第一和第二选择输出之间进行选择。 选择信号取决于序列中第一个已解析符号之前的先前解析符号。

公开(公告)号：US20240345646A1

公开(公告)日：2024-10-17

申请号：US18643714

申请日：2024-04-23

Applicant: Rambus Inc.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  H03L7/081

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G06F2205/067 ,  G11C7/04 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US11994930B2

公开(公告)日：2024-05-28

申请号：US17748704

申请日：2022-05-19

Applicant: Rambus Inc.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/04 ,  H03L7/081

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G06F2205/067 ,  G11C7/04 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US20240020258A1

公开(公告)日：2024-01-18

申请号：US18355660

申请日：2023-07-20

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

CPC classification number: G06F13/4022 ,  G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1694

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20220398206A1

公开(公告)日：2022-12-15

申请号：US17809688

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US11409682B2

公开(公告)日：2022-08-09

申请号：US16950861

申请日：2020-11-17

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20210141748A1

公开(公告)日：2021-05-13

申请号：US17081909

申请日：2020-10-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G06F13/40

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US20200026677A1

公开(公告)日：2020-01-23

申请号：US16525315

申请日：2019-07-29

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US10133338B2

公开(公告)日：2018-11-20

申请号：US15589651

申请日：2017-05-08

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G11C8/00 ,  G06F1/32 ,  G06F5/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22 ,  H03L7/081 ,  G11C7/04

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.