公开(公告)号：US09831093B2

公开(公告)日：2017-11-28

申请号：US15236472

申请日：2016-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kentaro Saito ,  Hideki Sugiyama ,  Hiraku Chakihara ,  Yoshiyuki Kawashima

IPC: H01L27/06 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11573 ,  H01L49/02

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

公开(公告)号：US09755012B2

公开(公告)日：2017-09-05

申请号：US15256285

申请日：2016-09-02

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

IPC: H01L49/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/108 ,  H01L27/11573 ,  H01L27/115

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US09461105B2

公开(公告)日：2016-10-04

申请号：US14636311

申请日：2015-03-03

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

IPC: H01L49/02 ,  H01L27/108 ,  H01L27/06 ,  H01L27/08 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US09412878B2

公开(公告)日：2016-08-09

申请号：US14738850

申请日：2015-06-13

Applicant: Renesas Electronics Corporation

Inventor： Koji Ogata ,  Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Tomohiro Hayashi

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/788 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11573 ,  H01L29/0607 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device having improved reliability is disclosed. In a semiconductor device according to one embodiment, an element isolation region extending in an X direction has a crossing region that crosses, in plan view, a memory gate electrode extending in a Y direction that intersects with the X direction at right angles. In this case, in the crossing region, a width in the Y direction of one edge side, the one edge side being near to a source region, is larger than a width in the Y direction of the other edge side, the other edge side being near to a control gate electrode.

Abstract translation: 公开了一种具有提高的可靠性的半导体器件。 在根据一个实施例的半导体器件中，沿X方向延伸的元件隔离区域具有在平面图中与在与X方向成直角相交的Y方向上延伸的存储栅电极的交叉区域。 在这种情况下，在交叉区域中，一个边缘侧的Y方向上的一个边缘侧靠近源极区域的宽度大于另一个边缘侧的Y方向上的宽度，另一个边缘侧 靠近控制栅电极。

公开(公告)号：US09379127B2

公开(公告)日：2016-06-28

申请号：US14745340

申请日：2015-06-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

公开(公告)号：US09324726B2

公开(公告)日：2016-04-26

申请号：US14802050

申请日：2015-07-17

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Kyoko Umeda ,  Akio Nishida

IPC: H01L21/336 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11573

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Abstract translation: 提高了半导体器件的性能。 在制造半导体器件的方法中，在存储单元区域中，在半导体衬底的主表面上形成由第一导电膜形成的控制栅电极。 然后，以覆盖控制栅电极的方式形成绝缘膜和第二导电膜，并且将第二导电膜回蚀刻。 结果，第二导电膜经由绝缘膜留在控制栅电极的侧壁上，从而形成存储栅电极。 然后，在外围电路区域中，在半导体衬底的主表面上形成p型阱。 在p型阱上形成第三导电膜。 然后，形成由第三导电膜形成的栅电极。

公开(公告)号：US20150380425A1

公开(公告)日：2015-12-31

申请号：US14738850

申请日：2015-06-13

Applicant: Renesas Electronics Corporation

Inventor： Koji Ogata ,  Yoshiyuki Kawashima ,  Hiraku Chakihara ,  Tomohiro Hayashi

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/51 ,  H01L29/08 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L29/788 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11573 ,  H01L29/0607 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device having improved reliability is disclosed. In a semiconductor device according to one embodiment, an element isolation region extending in an X direction has a crossing region that crosses, in plan view, a memory gate electrode extending in a Y direction that intersects with the X direction at right angles. In this case, in the crossing region, a width in the Y direction of one edge side, the one edge side being near to a source region, is larger than a width in the Y direction of the other edge side, the other edge side being near to a control gate electrode.

Abstract translation: 公开了具有可靠性提高的半导体器件。 在根据一个实施例的半导体器件中，沿X方向延伸的元件隔离区域具有在平面图中与在与X方向成直角相交的Y方向上延伸的存储栅电极的交叉区域。 在这种情况下，在交叉区域中，一个边缘侧的Y方向上的一个边缘侧靠近源极区域的宽度大于另一个边缘侧的Y方向上的宽度，另一个边缘侧 靠近控制栅电极。

公开(公告)号：US08592275B2

公开(公告)日：2013-11-26

申请号：US13888922

申请日：2013-05-07

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kawashima

IPC: H01L21/8239

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.

Abstract translation: 本发明的目的是提供一种具有高操作速度和高重写周期的非易失性存储单元和高可靠性的非易失性存储单元的半导体器件。 在其中存储栅电极形成为控制栅电极的侧壁形状的分离栅型非易失性存储器中，可以产生具有高操作速度和高重写周期的存储器和高存储器的存储芯片 通过在相同的芯片中共同加载具有不同存储器栅极长度的存储单元，以低成本的可靠性。