公开(公告)号：US08462908B2

公开(公告)日：2013-06-11

申请号：US12974949

申请日：2010-12-21

申请人： Ramanand Venkata ,  Chong H. Lee

发明人： Ramanand Venkata ,  Chong H. Lee

IPC分类号： H03D3/24

CPC分类号： H03M9/00 ,  H03L7/089 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0337

摘要： Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

摘要翻译： 锁相环电路以数字方式进行数字操作，至少在很大程度上从多个相位分布的候选时钟信号中选择最接近相位的信号，以便在诸如时钟数据恢复（“CDR”）信号的另一个信号中转换 。 该电路被构造和操作以避免由于候选时钟信号的选择变化而导致的输出时钟信号中的毛刺。 候选时钟信号的分频可以用于帮助电路以低于锁相环电路的模拟部分可以经济地提供的频率的比特率来支持串行通信。 出于同样的原因，发射侧可能会使用过量传输或过采样。

公开(公告)号：US07848318B2

公开(公告)日：2010-12-07

申请号：US11364589

申请日：2006-02-27

申请人： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

发明人： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

IPC分类号： H04Q11/00

CPC分类号： H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

摘要翻译： 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US07538578B2

公开(公告)日：2009-05-26

申请号：US11177034

申请日：2005-07-08

申请人： Ramanand Venkata ,  Chong H Lee ,  Rakesh H Patel

发明人： Ramanand Venkata ,  Chong H Lee ,  Rakesh H Patel

IPC分类号： H03K19/177 ,  G06F13/42

CPC分类号： H03K19/17744

摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.

摘要翻译： 用于可编程逻辑器件的串行接口可以根据各种通信协议进行操作，并且包括接收器部分和发射器部分。 接收器部分至少包括字或字节对准级，去偏移级，速率补偿或匹配级，填充协议解码器级（例如，8B / 10B解码器电路或64B / 66B解码器电路），字节解串器 阶段，字节重排阶段和相位补偿阶段。 发射机部分至少包括相位补偿级，字节解串器级和填充协议编码器级（例如，8B / 10B编码器电路或64B / 66B编码器电路）。 每个阶段可能有多次出现相关的电路。 选择电路，例如多路复用器，为所使用的协议选择适当的阶段和每个阶段内的电路。

公开(公告)号：US07362833B1

公开(公告)日：2008-04-22

申请号：US10609091

申请日：2003-06-27

申请人： Vinson Chan ,  Chong Lee ,  Rakesh Patel ,  Ramanand Venkata

发明人： Vinson Chan ,  Chong Lee ,  Rakesh Patel ,  Ramanand Venkata

IPC分类号： H04B1/10

CPC分类号： H04J3/0608

摘要： Circuitry for locating the boundaries of bytes in a data stream is provided. The data stream typically has comma or header information that provides an indication of the byte boundaries. When circuitry detects this information, it can align the byte boundaries and thereby provide byte-aligned data to utilization circuitry (e.g., a programmable logic device). In accordance with this invention, circuitry can select different special characters for use in detecting the byte boundaries, where the special characters are different lengths. Circuitry aligns the byte boundaries based on the selected special character when enabled by a control signal. Once aligned, circuitry can provide a signal indicating which special character was used to align the boundaries. Another advantage of the invention is that it eliminates alignment problems associated with system latency. Circuitry automatically locks alignment to a first instance of a detected special character independent of an external control signal.

摘要翻译： 提供了用于定位数据流中字节边界的电路。 数据流通常具有提供字节边界指示的逗号或头信息。 当电路检测到该信息时，它可以对齐字节边界，从而向利用电路（例如，可编程逻辑器件）提供字节对齐的数据。 根据本发明，电路可以选择用于检测字节边界的不同特殊字符，其中特殊字符是不同的长度。 当控制信号使能时，电路会根据所选择的特殊字符对齐字节边界。 一旦对准，电路可以提供一个信号，指示哪个特殊字符用于对齐边界。 本发明的另一个优点是它消除了与系统延迟相关联的对准问题。 电路自动将校准锁定到独立于外部控制信号的检测到的特殊字符的第一实例。

公开(公告)号：US07310399B1

公开(公告)日：2007-12-18

申请号：US11650163

申请日：2007-01-05

申请人： Ramanand Venkata ,  Chong H. Lee

发明人： Ramanand Venkata ,  Chong H. Lee

IPC分类号： H04L25/40

CPC分类号： G06F1/10

摘要： A programmable logic device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry. The HSSI circuitry includes clock signal circuitry that allows various components of the HSSI circuitry to be clocked in different ways to facilitate use of the HSSI circuitry to support a number of different communication protocols. Some of the HSSI clock signals may be routed through the clock distribution network of the associated PLD logic circuitry. The HSSI circuitry may include phase compensation buffer circuitry to compensate for possible phase differences across the interface between the HSSI circuitry and the associated PLD logic circuitry.

公开(公告)号：US07272677B1

公开(公告)日：2007-09-18

申请号：US10637982

申请日：2003-08-08

申请人： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

IPC分类号： G06F3/00 ,  G06F13/12

CPC分类号： H03K19/1774 ,  G06F1/12 ,  H03K19/17744 ,  H03K19/17792

摘要： A serial interface for a programmable logic device substantially eliminates skew across multiple channels both in the receiver and in the transmitter. Even when the channels are independent (e.g., are in different quads), skew is substantially eliminated by monitoring to determine when all channels have reached their active states (i.e., in the case of receiver channels when all channels have achieved byte alignment and have received an alignment character, and in the case of transmitter channels when all transmit PLLs have locked), and only then allowing data to flow between the serial and parallel domains.

摘要翻译： 用于可编程逻辑器件的串行接口基本上消除了接收器和发射器中的多个通道的偏移。 即使当信道是独立的（例如，处于不同的四边形）时，通过监视基本上消除了偏差，以便确定所有信道何时已经达到其活动状态（即，在所有信道已经实现字节对齐并已经接收到的信道的情况下 对齐字符，并且在所有发送PLL锁定时在发送器通道的情况下），并且仅允许数据在串行和并行域之间流动。

公开(公告)号：US20070058618A1

公开(公告)日：2007-03-15

申请号：US11288810

申请日：2005-11-28

申请人： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

发明人： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

IPC分类号： H04L12/50

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以促进诸如电路设计和验证的事情。

公开(公告)号：US20070043991A1

公开(公告)日：2007-02-22

申请号：US11359273

申请日：2006-02-21

申请人： Toan Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Tim Hoang ,  Ramanand Venkata ,  Chong Lee

发明人： Toan Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Tim Hoang ,  Ramanand Venkata ,  Chong Lee

IPC分类号： G01R31/28

CPC分类号： H03M9/00

摘要： Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

摘要翻译： 用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。 电路也可以在宽频率范围内的任何频率下工作。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US07180972B1

公开(公告)日：2007-02-20

申请号：US10273899

申请日：2002-10-16

申请人： Ramanand Venkata ,  Chong H Lee

发明人： Ramanand Venkata ,  Chong H Lee

IPC分类号： H04L7/00

CPC分类号： G06F1/10

摘要： A programmable logic device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry. The HSSI circuitry includes clock signal circuitry that allows various components of the HSSI circuitry to be clocked in different ways to facilitate use of the HSSI circuitry to support a number of different communication protocols. Some of the HSSI clock signals may be routed through the clock distribution network of the associated PLD logic circuitry. The HSSI circuitry may include phase compensation buffer circuitry to compensate for possible phase differences across the interface between the HSSI circuitry and the associated PLD logic circuitry.

摘要翻译： 可编程逻辑器件（“PLD”）包括高速串行接口（“HSSI”）电路。 HSSI电路包括时钟信号电路，其允许HSSI电路的各种组件以不同的方式计时，以便于使用HSSI电路来支持多种不同的通信协议。 一些HSSI时钟信号可以通过相关联的PLD逻辑电路的时钟分配网络路由。 HSSI电路可以包括相位补偿缓冲器电路，以补偿跨越HSSI电路和相关联的PLD逻辑电路之间的接口上的可能的相位差。

公开(公告)号：US07131024B1

公开(公告)日：2006-10-31

申请号：US10670813

申请日：2003-09-24

申请人： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

IPC分类号： G06F1/06

CPC分类号： G06F1/06

摘要： A serial interface for a programmable logic device provides multiple data rates in different channels by generating a central serial clock and providing at least one divider in each channel that can divide the central clock by different integer values. For additional variation in clock rate, two or more different central clocks can be provided, with each channel then being able to divide any of the central clocks to provide the desired local clock. Lower speed parallel clocks can be generated locally by further dividing the divided serial clock. Alternatively, the central serial clock or clocks may be divided centrally to provide a central parallel clock or clocks which can then be used locally as a local parallel clock.

摘要翻译： 用于可编程逻辑器件的串行接口通过产生中央串行时钟来在不同的通道中提供多个数据速率，并且在每个通道中提供至少一个可以将中心时钟除以不同整数值的分频器。 对于时钟速率的额外变化，可以提供两个或多个不同的中央时钟，每个信道然后能够分割任何中央时钟以提供期望的本地时钟。 可以通过进一步分割串行时钟来本地生成低速并行时钟。 或者，中央串行时钟可以集中分配以提供中央并行时钟或时钟，然后可以将其本地地用作本地并行时钟。