公开(公告)号：US20180261266A1

公开(公告)日：2018-09-13

申请号：US15889191

申请日：2018-02-05

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/02 ,  G11C7/08 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US10074417B2

公开(公告)日：2018-09-11

申请号：US15522182

申请日：2015-11-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  James E. Harris

IPC: G11C7/22 ,  G11C11/4093 ,  G11C8/12 ,  G11C5/06 ,  G11C5/04

CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C8/12

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

公开(公告)号：US09911468B2

公开(公告)日：2018-03-06

申请号：US15390674

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20170310910A1

公开(公告)日：2017-10-26

申请号：US15589149

申请日：2017-05-08

Applicant: Rambus Inc.

Inventor： Craig M. Smith ,  Michael Guidash ,  Jay Endsley ,  Thomas Vogelsang ,  James E. Harris

IPC: H04N5/355 ,  H04N5/3745 ,  H04N5/347 ,  H01L27/146 ,  H04N5/378 ,  H04N5/374

CPC classification number: H04N5/3559 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14645 ,  H04N5/347 ,  H04N5/355 ,  H04N5/3741 ,  H04N5/37455 ,  H04N5/378

Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.

公开(公告)号：US09521337B1

公开(公告)日：2016-12-13

申请号：US13936985

申请日：2013-07-08

Applicant: Rambus Inc.

Inventor： Jie Shen ,  Yueyong Wang ,  James E. Harris

IPC: H01L27/00 ,  H04N5/335 ,  H04N5/235 ,  H04N5/353 ,  H04N5/355

CPC classification number: H04N5/3355 ,  H04N5/2353 ,  H04N5/3535 ,  H04N5/355 ,  H04N5/3745 ,  H04N5/37455

Abstract: A self-resetting pixel having a memory element to record occurrence of an asynchronous pixel reset and circuitry to enable the memory element to be digitally sampled and cleared is disclosed, together with embodiments of digital image sensors formed by arrays or other collections of such pixels. By marking occurrence of asynchronous reset events within an in-pixel memory element that may be digitally oversampled during an exposure interval (i.e., repeatedly read-out in the form of, for example, a single-bit), it becomes possible to check for and detect asynchronous pixel reset events frequently and efficiently.

Abstract translation: 公开了具有用于记录异步像素复位的存储元件以及使存储器元件能够被数字采样和清除的电路的自复位像素，以及由这些像素的阵列或其他集合形成的数字图像传感器的实施例。 通过标记可能在曝光间隔期间被数字过采样的像素内存储元件内的异步复位事件的出现（例如，以例如单位形式重复读出），可以检查 并频繁且高效地检测异步像素复位事件。

公开(公告)号：US20160307609A1

公开(公告)日：2016-10-20

申请号：US15138424

申请日：2016-04-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/12 ,  G11C7/22 ,  G11C7/06

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US09344635B2

公开(公告)日：2016-05-17

申请号：US14355799

申请日：2012-11-08

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  David Geoffrey Stork ,  John Eric Linstadt ,  James E. Harris

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/235 ,  H04N5/355 ,  H04N5/3745 ,  H04N5/353 ,  H04N1/00

CPC classification number: H04N5/235 ,  H04N1/00769 ,  H04N5/2355 ,  H04N5/3355 ,  H04N5/3535 ,  H04N5/355 ,  H04N5/35536 ,  H04N5/3745

Abstract: Pixel circuits in an image sensor are sampled repetitively during an image frame period. At each sampling, a signal indicative of the photocharge integrated by a pixel circuit since last reset is compared to a threshold. If the integrated photocharge signal has not reached the threshold, the pixel circuit is permitted to continue integrating photocharge. If the integrated photocharge signal has reached the threshold, the pixel circuit is reset to remove integrated photocharge and photocharge integration for that pixel circuit is restarted. A corresponding pixel circuit value is recorded for the reset pixel circuit.

Abstract translation: 图像传感器中的像素电路在图像帧周期期间重复采样。 在每次采样时，将与上一次复位后的像素电路集成的光电荷的信号与阈值进行比较。 如果集成光电荷信号尚未达到阈值，则允许像素电路继续积分光电荷。 如果积分的光电荷信号已经达到阈值，则像素电路被复位以去除集成的光电荷并且该像素电路的光电荷积分被重新启动。 记录复位像素电路的对应像素电路值。

公开(公告)号：US20150070544A1

公开(公告)日：2015-03-12

申请号：US14482065

申请日：2014-09-10

Applicant: Rambus Inc.

Inventor： Craig M. Smith ,  Michael Guidash ,  Jay Endsley ,  Thomas Vogelsang ,  James E. Harris

IPC: H04N5/378

CPC classification number: H04N5/3559 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14645 ,  H04N5/347 ,  H04N5/355 ,  H04N5/3741 ,  H04N5/37455 ,  H04N5/378

Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.

Abstract translation: 在集成电路图像传感器内的像素阵列中，评估多个像素中的每一个以确定响应于入射光在像素内积分的电荷是否超过第一阈值。 产生与集成在多个像素的至少一个子集中的电荷相对应的N位数字样本，然后将其应用于查找表以检索相应的M位数字值（M小于N），其中步长范围 由M位数字值的可能状态表示的电荷积分电平从基于第一阈值确定的起始电荷积分电平向上延伸。

公开(公告)号：US20140016423A1

公开(公告)日：2014-01-16

申请号：US13938130

申请日：2013-07-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness ,  Ian P. Shaeffer ,  James E. Harris

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/1009 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40622

Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

Abstract translation: 诸如存储器控制器和存储器设备的存储器系统的组件通过控制存储器件的刷新定时来减少退出自刷新模式的延迟。 存储器件包括存储器核。 存储装置的接口电路接收指示间歇刷新事件的外部刷新信号。 存储器件的刷新电路产生指示存储器件的内部刷新事件的内部刷新信号。 存储器件的刷新控制电路响应于内部刷新事件，在相对于由外部刷新信号指示的间歇刷新事件的时间，对存储器核心的一部分执行刷新操作。