公开(公告)号：US12154635B2

公开(公告)日：2024-11-26

申请号：US17410265

申请日：2021-08-24

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Henry Chin ,  Erika Penzo

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.

公开(公告)号：US11894081B2

公开(公告)日：2024-02-06

申请号：US17685113

申请日：2022-03-02

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Xue Bai Pitner ,  Ken Oowada

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26

Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a magnitude of a boosting voltage bias (VPASS) that is to be applied to an unselected word line may be determined according to the determined total number of erase/programming (EP) cycles.

公开(公告)号：US20230223084A1

公开(公告)日：2023-07-13

申请号：US17571124

申请日：2022-01-07

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Fanqi Wu ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C7/10

CPC classification number: G11C16/102 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C7/1048

Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.

公开(公告)号：US20230146549A1

公开(公告)日：2023-05-11

申请号：US17522414

申请日：2021-11-09

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Tai-Yuan Tseng

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074

CPC classification number: G11C11/4096 ,  G11C11/4087 ,  G11C11/4085 ,  G11C11/4076 ,  G11C11/4074

Abstract: A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.

公开(公告)号：US20230069260A1

公开(公告)日：2023-03-02

申请号：US17461922

申请日：2021-08-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Tomer Eliash

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.

公开(公告)号：US20220383961A1

公开(公告)日：2022-12-01

申请号：US17329390

申请日：2021-05-25

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Tomer Eliash ,  Huai-Yuan Tseng

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

公开(公告)号：US11475959B1

公开(公告)日：2022-10-18

申请号：US17363419

申请日：2021-06-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Sujjatul Islam ,  Xue Pitner

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/24 ,  G11C11/56 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/08

Abstract: Apparatuses and techniques are described for reducing the program time for a set of memory cells by using an enhanced step up of a program bias. A program operation includes a first pass in which memory cells are programmed to intermediate states and a second program pass in which the memory cells are programmed from an erased state and the intermediate states to final states. In the first program pass, program time can be reduced by applying an enhanced program bias step up to memory cells of the highest intermediate state in a single program loop, for example. The enhanced program bias step up can be achieved by applying a negative bit line voltage and can be triggered when the memory cells assigned to the second highest intermediate state reach a program milestone such as completing programming.

公开(公告)号：US11417400B2

公开(公告)日：2022-08-16

申请号：US16778821

申请日：2020-01-31

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/00 ,  G11C16/26 ,  H01L27/11556 ,  G11C5/06 ,  G11C16/10 ,  G11C5/02 ,  H01L27/11582

Abstract: Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.

公开(公告)号：US11361835B1

公开(公告)日：2022-06-14

申请号：US17188998

申请日：2021-03-01

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Fanglin Zhang ,  Huai-Yuan Tseng

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

Abstract: Apparatuses and techniques are described for avoiding current consumption peaks during a program operation for a memory device. The timing of scan operations of latches is adjusted to avoid overlapping with an increase in word line voltages. The scan operations can include a pre-charge select scan, which identifies memory cells subject to a verify test, and a fill operation for latches of memory cells which fail a verify test in a prior program loop. The pre-charge select scan can occur before the increase in the word line voltages, while the fill operation occurs after the increase in word line voltages. In another approach, the start of the increase in the word line voltages is delayed when a state bit scan is expected to take a relatively long time, e.g., when a verify test is passed in a prior program loop.

公开(公告)号：US11270776B1

公开(公告)日：2022-03-08

申请号：US17116836

申请日：2020-12-09

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/24 ,  G11C16/08

Abstract: Apparatuses and techniques are described for reducing a peak current consumption during a program operation for a memory device. A higher current peak occurs in a first program loop of the program operation when a set of word lines is in a discharged state, also referred to as a first read condition. A current reduction countermeasure can be used when ramping up voltages of unselected word lines to a read pass voltage during the verify phase of the program loop. The countermeasure can involve reducing the ramp up rate, reducing the read pass voltage, or delaying the start of the ramp up for a portion of the word lines.