公开(公告)号：US20250008741A1

公开(公告)日：2025-01-02

申请号：US18691160

申请日：2022-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE ,  Ryota HODO ,  Yasuhiro JINBO

IPC: H10B53/30

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a first electrode, a transistor including a back gate, a capacitor including a pair of electrodes, and a first insulator that can have ferroelectricity between the back gate of the transistor and a semiconductor. The first insulator overlaps with the semiconductor with a second insulator therebetween. One of a source electrode and a drain of the transistor is electrically connected to the first electrode. The other of the source and the drain of the transistor is electrically connected to one electrode of the pair of electrodes. The pair of electrodes are each in contact with the first insulator and include a region where the pair of electrodes overlap with each other with the first insulator therebetween. As the first insulator, a ferroelectric is used.

公开(公告)号：US20240298447A1

公开(公告)日：2024-09-05

申请号：US18658092

申请日：2024-05-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Hitoshi KUNITAKE ,  Kazuki TSUDA

IPC: H10B43/27 ,  G11C16/04 ,  G11C16/08 ,  H10B41/27

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/08 ,  H10B41/27

Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.

公开(公告)号：US20240105855A1

公开(公告)日：2024-03-28

申请号：US18530797

申请日：2023-12-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Hitoshi KUNITAKE

IPC: H01L29/786 ,  H01L27/10 ,  H10B12/00 ,  H10B41/27 ,  H10B43/30

CPC classification number: H01L29/7869 ,  H01L27/10 ,  H10B12/30 ,  H10B41/27 ,  H10B43/30

Abstract: A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.

公开(公告)号：US20230380180A1

公开(公告)日：2023-11-23

申请号：US18030334

申请日：2021-10-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tomonori NAKAYAMA ,  Masahiro TAKAHASHI ,  Hitoshi KUNITAKE

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A ferroelectric device (100) that includes a metal nitride film (130) with favorable ferroelectricity is provided. The ferroelectric device comprises a first conductor (110), a metal nitride film over the first conductor, a second conductor (120) over the metal nitride film, a first insulator (155) over the second conductor, and a second insulator (152) over the first insulator. The first insulator includes regions in contact with the side surface of the metal nitride film and the side surface and the top surface of the second conductor; the metal nitride film has ferroelectricity; the metal nitride film contains a first element, a second element, and nitrogen; the first element is one or more elements selected from Group 13 elements; the second element is one or more elements selected from Group 2 elements to Group 6 elements and Group 13 elements other than the first element; the first conductor and the second conductor each contain nitrogen; the first insulator contains aluminum and oxygen; and the second insulator contains silicon and nitrogen.

公开(公告)号：US20230301099A1

公开(公告)日：2023-09-21

申请号：US18013917

申请日：2021-07-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Yuki ITO ,  Shunpei YAMAZAKI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A novel semiconductor device is provided. The semiconductor device includes an oxide semiconductor as a first semiconductor, silicon as a second semiconductor, and a plurality of memory cells lined up in a first direction; and a memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, part of the first semiconductor functions as a channel formation region of the writing transistor, and part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.

公开(公告)号：US20220406347A1

公开(公告)日：2022-12-22

申请号：US17772331

申请日：2020-08-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Hitoshi KUNITAKE

IPC: G11C7/10

Abstract: A data device with a small circuit area and reduced power consumption is used. The data processing device includes a NAND memory portion and a controller. The memory portion includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell.

公开(公告)号：US20220352865A1

公开(公告)日：2022-11-03

申请号：US17765046

申请日：2020-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki OHSHIMA ,  Hitoshi KUNITAKE ,  Yuto YAKUBO ,  Takayuki IKEDA

IPC: H03H7/38 ,  H01L21/822 ,  H01L21/02 ,  H03F3/60 ,  H03F3/19 ,  H01L27/088

Abstract: An amplifier is formed in a wiring layer. A semiconductor device includes a second layer over a first layer with a metal oxide therebetween. The first layer includes a first transistor including a first semiconductor layer containing silicon. The second layer includes an impedance matching circuit, and the impedance matching circuit includes a second transistor including a second semiconductor layer containing gallium. The first transistor forms first coupling capacitance between the first transistor and the metal oxide, and the impedance matching circuit forms second coupling capacitance between the impedance matching circuit and the metal oxide. The impedance matching circuit is electrically connected to the metal oxide through the second coupling capacitance. The metal oxide inhibits the influence of first radiation noise emitted from the impedance matching circuit on the operation of the first transistor.

公开(公告)号：US20220350571A1

公开(公告)日：2022-11-03

申请号：US17778134

申请日：2020-11-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Takayuki IKEDA ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE

IPC: G06F7/544 ,  G11C11/405 ,  G11C11/4096 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A novel information processing device with least signal transmission delay and low power consumption is provided. A storage device includes a first layer, a second layer, and a third layer. The first layer is provided with a circuit. The second layer is provided with a memory cell portion. The third layer is provided with a first electrode. The circuit has a function of switching and performing reading or writing of first data or second data from or to the memory cell portion. At least part of the second layer is stacked above the first layer. At least part of the third layer is stacked above the second layer. An arithmetic device includes a fourth layer and a fifth layer. The fourth layer is provided with a central processing device. The fifth layer is provided with a second electrode. At least part of the fifth layer is stacked above the fourth layer. The circuit is electrically connected to the central processing device through the first electrode and the second electrode.

公开(公告)号：US20220262858A1

公开(公告)日：2022-08-18

申请号：US17629804

申请日：2020-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Hideki UOCHI ,  Satoru OKAMOTO ,  Hiromichi GODO ,  Kazuki TSUDA ,  Hitoshi KUNITAKE

IPC: H01L27/24

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US20220236785A1

公开(公告)日：2022-07-28

申请号：US17614409

申请日：2020-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takahiko ISHIZU ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE

IPC: G06F1/3287 ,  H01L27/108 ,  H01L27/11

Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a power management unit, a CPU core, and a memory device, the power management unit includes a power switch and a power controller, and the memory device includes a working memory and a long-term memory storage portion. The power switch has a function of controlling supply of a power supply voltage to the CPU core and the memory device, and the power controller has a function of controlling operation of the power switch. The CPU core has a function of transmitting a timing of stopping the supply of the power supply voltage to the power controller, and the memory device has a function of saving data retained in the working memory to the long-term memory storage portion before the supply of the power supply voltage is stopped by the power switch. Transistors included in each of the power management unit and the CPU core are preferably Si transistors.