公开(公告)号：US11882707B2

公开(公告)日：2024-01-23

申请号：US17559821

申请日：2021-12-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H10B63/00 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/10 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/32 ,  H01L21/8222 ,  H01L27/0823 ,  H01L29/1004 ,  H10B63/80 ,  H10N70/231 ,  H10N70/826

Abstract: The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.

公开(公告)号：US11875847B2

公开(公告)日：2024-01-16

申请号：US17673550

申请日：2022-02-16

Applicant: Universite D'Aix Marseille ,  Centre National De La Recherche Scientifique ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Jean-Michel Portal ,  Vincenzo Della Marca ,  Jean-Pierre Walder ,  Julien Gasquez ,  Philippe Boivin

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0054 ,  G11C2213/72

Abstract: Memory devices such as phase change memory (PCM) devices utilizing Ovonic Threshold Switching (OTS) selectors may be used to fill the gap between dynamic random-access memory (DRAM) and mass storage and may be incorporated in high-end microcontrollers. Since the programming efficiency and reading phase efficiency of such devices is directly linked to the leakage current of the OTS selector as well as sneak-path management, a sense amplifier disclosed herein generates an auto-reference that takes into account the leakage currents of unselected cells and includes a regulation loop to compensate for voltage drop due to read current sensing. This auto-referenced sense amplifier, built utilizing the principle of charge-sharing, may be designed on a 28 nm fully depleted silicon-on-insulator (FDSOI) technology, provides robust performance for a wide range of sneak-path currents and consequently for a large range of memory array sizes, and is therefore suitable for use in embedded memory in high-end microcontroller.

公开(公告)号：US11152430B2

公开(公告)日：2021-10-19

申请号：US16375571

申请日：2019-04-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Jean Jacques Fagot ,  Emmanuel Petitprez ,  Emeline Souchier ,  Olivier Weber

IPC: H01L29/73 ,  H01L27/24 ,  H01L45/00

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US11114614B2

公开(公告)日：2021-09-07

申请号：US16400649

申请日：2019-05-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H01L45/00 ,  H01L27/24

Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.

公开(公告)号：US10431630B2

公开(公告)日：2019-10-01

申请号：US15436963

申请日：2017-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Jean-Jacques Fagot

IPC: H01L27/24 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L45/00 ,  H01L21/28

Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.

公开(公告)号：US20180175022A1

公开(公告)日：2018-06-21

申请号：US15897524

申请日：2018-02-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L27/24 ,  H01L21/84 ,  H01L29/732 ,  H01L45/00 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1207 ,  H01L27/2445 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/66303 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US20180076265A1

公开(公告)日：2018-03-15

申请号：US15436963

申请日：2017-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Jean-Jacques Fagot

IPC: H01L27/24 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/423 ,  H01L45/00

Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.

公开(公告)号：US20170317275A1

公开(公告)日：2017-11-02

申请号：US15654405

申请日：2017-07-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1666

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

公开(公告)号：US20170317106A1

公开(公告)日：2017-11-02

申请号：US15361937

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Franck Arnaud ,  Gregory Bidal ,  Dominique Golanski ,  Emmanuel Richard

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L27/1207 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4916

Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.

公开(公告)号：US09793321B2

公开(公告)日：2017-10-17

申请号：US14970347

申请日：2015-12-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.