公开(公告)号：US20150019885A1

公开(公告)日：2015-01-15

申请号：US14446814

申请日：2014-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Fabrice Marinet

IPC: G06F1/26 ,  H03K3/84 ,  H03K19/003 ,  H01L21/762

CPC classification number: G06F1/26 ,  G06F21/72 ,  G06K19/07309 ,  H01L21/76224 ,  H01L23/576 ,  H01L2924/0002 ,  H03K3/84 ,  H03K19/003 ,  H04L9/004 ,  H04L2209/12 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Abstract translation: 本公开涉及一种电子微电路中的对策方法，包括由微电路的电路执行的连续处理阶段，以及根据为该电路产生的随机值调整电路与电路的接地端之间的电源电压 处理阶段，在电路执行的每个处理阶段。

公开(公告)号：US11742050B2

公开(公告)日：2023-08-29

申请号：US17839168

申请日：2022-06-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice Romain ,  Mathieu Lisart

IPC: G11C29/44 ,  G11C29/14 ,  G11C29/42

CPC classification number: G11C29/44 ,  G11C29/14 ,  G11C29/42 ,  G11C2029/4402

Abstract: A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.

公开(公告)号：US20220199632A1

公开(公告)日：2022-06-23

申请号：US17540029

申请日：2021-12-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H01L27/112

Abstract: The present description concerns a ROM including at least one first rewritable memory cell.

公开(公告)号：US20210405100A1

公开(公告)日：2021-12-30

申请号：US17322140

申请日：2021-05-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Mathieu Dumont ,  Nicolas Borrel ,  Mathieu Lisart

IPC: G01R29/08 ,  G06F21/55 ,  G06F21/75

Abstract: An embodiment integrated circuit includes a first electromagnetic pulse detection device that comprises a first loop antenna formed in an interconnection structure of the integrated circuit, a first end of the first antenna being connected to a first node of application of a power supply potential and a second end of the antenna being coupled to a second node of application of the power supply potential, and a first circuit connected to the second end of the first antenna and configured to output a first signal representative of a comparison of a first current in the first antenna with a first threshold.

公开(公告)号：US20180277496A1

公开(公告)日：2018-09-27

申请号：US15784883

申请日：2017-10-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Raul Andres Bianchi ,  Benoit Froment

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/528 ,  H03K17/14 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3205 ,  G06F9/44

Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.

公开(公告)号：US20180233460A1

公开(公告)日：2018-08-16

申请号：US15788611

申请日：2017-10-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Benoit Froment

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  G01R31/02

CPC classification number: H01L23/573 ,  G01R31/028 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/576 ,  H01L23/642 ,  H01L25/16

Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.

公开(公告)号：US20180145027A1

公开(公告)日：2018-05-24

申请号：US15596877

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/7685 ,  H01L21/76883 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/573

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.

公开(公告)号：US20170323859A1

公开(公告)日：2017-11-09

申请号：US15661369

申请日：2017-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Nicolas Borrel

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/64 ,  H03K17/687

CPC classification number: H01L23/576 ,  G01R31/2851 ,  G01R31/44 ,  G06F21/6245 ,  H01L22/34 ,  H01L23/647 ,  H03K17/687

Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.

公开(公告)号：US09754902B2

公开(公告)日：2017-09-05

申请号：US15072209

申请日：2016-03-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Nicolas Borrel

IPC: H01L23/58 ,  H01L23/00 ,  H03K17/687 ,  H01L21/66 ,  H01L23/64

CPC classification number: H01L23/576 ,  G01R31/2851 ,  G01R31/44 ,  G06F21/6245 ,  H01L22/34 ,  H01L23/647 ,  H03K17/687

Abstract: An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second conductivity type arranged in alternated and contiguous fashion on a region of the second conductivity type, including for each of the first strips: a plurality of bias contacts; for each bias contact, a switch capable of applying a potential on the bias contact; two detection contacts arranged at the ends of the first strip; and a detection circuit having its activation causing the turning off of the switches and the comparison with a threshold of the resistance between the detection contacts.

公开(公告)号：US09012911B2

公开(公告)日：2015-04-21

申请号：US14085565

申请日：2013-11-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sylvie Wuidart ,  Mathieu Lisart ,  Alexandre Sarafianos

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/576 ,  G06F21/75 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L2924/0002 ,  Y10T307/76 ,  H01L2924/00

Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.

Abstract translation: 一种集成电路，包括：第一导电类型的半导体衬底; 所述第一导电类型的多个区域从所述基板的表面垂直延伸，每个所述区域沿着其外围沿着所述第二导电类型的区域横向界定; 以及用于检测第一导电类型的每个区域和用于将衬底偏压的区域之间的衬底电阻变化为参考电压的装置。